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49faf0a1ac
Summary: In the case of an fp_extend of v1f16 to v1f32 where the v1f16 is the result of a bitcast from i16, avoid creating an illegal fp16_to_fp where the input is not a vector and the result is a v1f32. V2: The fix is now to avoid vector scalarization creating a v1->scalar bitcast. Reviewers: srhines, t.p.northover Subscribers: nhaehnle, llvm-commits, dstuttard, t-tye, yaxunl, wdng, kzhuravl, arsenm Differential Revision: https://reviews.llvm.org/D41126 llvm-svn: 322120
27 lines
955 B
LLVM
27 lines
955 B
LLVM
; RUN: llc -march=amdgcn -mcpu=gfx600 -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -march=amdgcn -mcpu=gfx700 -verify-machineinstrs < %s | FileCheck %s
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; On gfx6 and gfx7, this test shows a bug in SelectionDAG where scalarizing the
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; extension of a vector of f16 generates an illegal node that errors later.
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; CHECK-LABEL: {{^}}main:
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; CHECK: v_cvt_f32_f16
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define amdgpu_gs void @main(i32 inreg %arg) local_unnamed_addr #0 {
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.entry:
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%tmp = load volatile float, float addrspace(1)* undef
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%tmp1 = bitcast float %tmp to i32
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%im0.i = lshr i32 %tmp1, 16
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%tmp2 = insertelement <2 x i32> undef, i32 %im0.i, i32 1
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%tmp3 = trunc <2 x i32> %tmp2 to <2 x i16>
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%tmp4 = bitcast <2 x i16> %tmp3 to <2 x half>
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%tmp5 = fpext <2 x half> %tmp4 to <2 x float>
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%bc = bitcast <2 x float> %tmp5 to <2 x i32>
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%tmp6 = extractelement <2 x i32> %bc, i32 1
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store volatile i32 %tmp6, i32 addrspace(1)* undef
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ret void
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}
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attributes #0 = { nounwind }
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