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262321d1ff
This patch lets the llvm tools handle the new HVX target features that
are added by frontend (clang). The target-features are of the form
"hvx-length64b" for 64 Byte HVX mode, "hvx-length128b" for 128 Byte mode HVX.
"hvx-double" is an alias to "hvx-length128b" and is soon will be deprecated.
The hvx version target feature is upgated form "+hvx" to "+hvxv{version_number}.
Eg: "+hvxv62"
For the correct HVX code generation, the user must use the following
target features.
For 64B mode: "+hvxv62" "+hvx-length64b"
For 128B mode: "+hvxv62" "+hvx-length128b"
Clang picks a default length if none is specified. If for some reason,
no hvx-length is specified to llvm, the compilation will bail out.
There is a corresponding clang patch.
Differential Revision: https://reviews.llvm.org/D38851
llvm-svn: 316101
144 lines
5.2 KiB
LLVM
144 lines
5.2 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check for a sane output. This testcase used to cause a crash.
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; CHECK: vlut16
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target triple = "hexagon-unknown--elf"
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declare void @halide_malloc() local_unnamed_addr #0
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declare <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32>) #1
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declare <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32>) #1
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declare <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32>, <32 x i32>) #1
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declare <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32>, <32 x i32>) #1
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declare <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32>, <64 x i32>) #1
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declare <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32>, <32 x i32>, i32) #1
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declare <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32>, <32 x i32>, i32) #1
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declare <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32>, <32 x i32>, <32 x i32>, i32) #1
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define hidden void @fred() #0 {
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b0:
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%v1 = ashr i32 undef, 7
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%v2 = shl nsw i32 %v1, 7
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switch i32 undef, label %b7 [
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i32 1, label %b3
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i32 2, label %b5
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i32 3, label %b6
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]
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b3: ; preds = %b0
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unreachable
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b4: ; preds = %b7
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switch i32 undef, label %b9 [
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i32 1, label %b8
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i32 2, label %b10
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i32 3, label %b11
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]
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b5: ; preds = %b0
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unreachable
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b6: ; preds = %b0
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unreachable
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b7: ; preds = %b0
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br label %b4
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b8: ; preds = %b4
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br label %b12
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b9: ; preds = %b4
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br label %b12
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b10: ; preds = %b4
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br label %b12
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b11: ; preds = %b4
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br label %b12
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b12: ; preds = %b11, %b10, %b9, %b8
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br label %b13
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b13: ; preds = %b14, %b12
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br label %b14
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b14: ; preds = %b13
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br i1 undef, label %b15, label %b13
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b15: ; preds = %b14
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br label %b16
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b16: ; preds = %b15
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br i1 undef, label %b17, label %b18
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b17: ; preds = %b16
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unreachable
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b18: ; preds = %b16
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tail call void @halide_malloc()
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br label %b19
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b19: ; preds = %b18
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br i1 undef, label %b20, label %b21
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b20: ; preds = %b19
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br label %b32
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b21: ; preds = %b38, %b19
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%v22 = zext i32 %v2 to i64
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%v23 = lshr i64 %v22, 31
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%v24 = shl nuw nsw i64 %v23, 1
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%v25 = or i64 %v24, 0
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%v26 = icmp ult i64 undef, 2147483648
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%v27 = mul nuw nsw i64 %v25, 3
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%v28 = add nuw nsw i64 %v27, 0
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%v29 = and i64 %v28, 133143986176
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%v30 = icmp eq i64 %v29, 0
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%v31 = and i1 %v26, %v30
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br label %b39
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b32: ; preds = %b20
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%v33 = zext i32 %v2 to i64
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%v34 = mul nuw nsw i64 %v33, 12
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%v35 = icmp ult i64 %v34, 2147483648
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%v36 = and i1 %v35, undef
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br i1 %v36, label %b38, label %b37
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b37: ; preds = %b32
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ret void
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b38: ; preds = %b32
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tail call void @halide_malloc()
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br label %b21
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b39: ; preds = %b42, %b21
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br label %b40
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b40: ; preds = %b39
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br i1 %v31, label %b42, label %b41
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b41: ; preds = %b40
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unreachable
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b42: ; preds = %b40
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%v43 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.128B(<32 x i32> undef, <32 x i32> undef, i32 0)
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%v44 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v43, <32 x i32> undef, <32 x i32> undef, i32 1)
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%v45 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v44, <32 x i32> undef, <32 x i32> undef, i32 2)
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%v46 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v45, <32 x i32> undef, <32 x i32> undef, i32 3)
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%v47 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v46, <32 x i32> undef, <32 x i32> undef, i32 4)
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%v48 = tail call <64 x i32> @llvm.hexagon.V6.vlutvwh.oracc.128B(<64 x i32> %v47, <32 x i32> undef, <32 x i32> undef, i32 5)
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%v49 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v48)
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%v50 = tail call <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32> undef, <32 x i32> %v49) #2
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%v51 = tail call <64 x i32> @llvm.hexagon.V6.vcombine.128B(<32 x i32> undef, <32 x i32> %v50) #2
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%v52 = tail call <64 x i32> @llvm.hexagon.V6.vaddw.dv.128B(<64 x i32> %v51, <64 x i32> undef) #2
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%v53 = tail call <32 x i32> @llvm.hexagon.V6.hi.128B(<64 x i32> %v52) #2
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%v54 = tail call <32 x i32> @llvm.hexagon.V6.vasrwhsat.128B(<32 x i32> %v53, <32 x i32> undef, i32 15) #2
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store <32 x i32> %v54, <32 x i32>* undef, align 128
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br label %b39
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}
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length128b" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind }
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