Jakob Stoklund Olesen 43f9c539ae Infer instruction properties from single-instruction patterns. ... Previously, instructions without a primary patterns wouldn't get their properties inferred. Now, we use all single-instruction patterns for inference, including 'def : Pat<>' instances. This causes a lot of instruction flags to change. - Many instructions no longer have the UnmodeledSideEffects flag because their flags are now inferred from a pattern. - Instructions with intrinsics will get a mayStore flag if they already have UnmodeledSideEffects and a mayLoad flag if they already have mayStore. This is because intrinsics properties are linear. - Instructions with atomic_load patterns get a mayStore flag because atomic loads can't be reordered. The correct workaround is to create pseudo-instructions instead of using normal loads. PR13693. llvm-svn: 162614		2012-08-24 22:46:53 +00:00
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ARM	Rejected 169195. As Duncan commented, bitcasting to proper type is wrong approach. We need to insert some valid TRANCATE node here.	2012-08-22 09:33:55 +00:00
CellSPU	Add test triples to fix win32 failures. Revert workaround from r161292.	2012-08-08 20:31:37 +00:00
CPP	test commit	2012-07-18 17:53:05 +00:00
Generic	BranchProb: modify the definition of an edge in BranchProbabilityInfo to handle	2012-08-24 18:14:27 +00:00
Hexagon	Infer instruction properties from single-instruction patterns.	2012-08-24 22:46:53 +00:00
MBlaze
Mips	Disable Mips' delay slot filler when optimization level is O0.	2012-08-24 20:40:15 +00:00
MSP430	Reapply r161633-161634 "Partition use lists so defs always come before uses.""	2012-08-10 00:21:30 +00:00
NVPTX
PowerPC	Lower constant pools and jump tables via TOC on PPC64/SVR4.	2012-08-24 16:26:02 +00:00
SPARC	test/CodeGen/SPARC/private.ll: Fixup. Forgot to prune old RUN lines.	2012-07-03 04:29:20 +00:00
Thumb
Thumb2	Add ADD and SUB to the predicable ARM instructions.	2012-08-16 23:21:55 +00:00
X86	fix a case where all operands of BUILD_VECTOR are undefined	2012-08-20 17:59:18 +00:00
XCore