Daniel Sanders e04bb135ee [mips] Merge disassemblers into a single implementation. ... Summary: Currently we have Mips32 and Mips64 disassemblers and this causes the target triple to affect the disassembly despite all the relevant information being in the ELF header. These implementations do not need to be separate. This patch merges them together such that the appropriate tables are checked for the subtarget (e.g. Mips64 is checked when GP64 is enabled). Reviewers: vmedic Reviewed By: vmedic Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D7498 llvm-svn: 228825		2015-02-11 11:28:56 +00:00
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AArch64
ARM
Hexagon	[Hexagon] Adding missing vector multiply instruction encodings. Converting multiply intrinsics and updating tests.	2015-02-03 19:15:11 +00:00
Mips	[mips] Merge disassemblers into a single implementation.	2015-02-11 11:28:56 +00:00
PowerPC	This change implements the following three logical vector operations:	2015-02-09 17:03:18 +00:00
Sparc
SystemZ
X86	[X86] Add GETSEC instruction.	2015-02-07 23:36:36 +00:00
XCore