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llvm-mirror/test/CodeGen/MIR/X86/expected-number-after-bb.mir
Alex Lorenz 813af3fadc MIR Parser: Verify the implicit machine register operands.
This commit verifies that the parsed machine instructions contain the implicit
register operands as specified by the MCInstrDesc. Variadic and call
instructions aren't verified.

Reviewers: Duncan P. N. Exon Smith

Differential Revision: http://reviews.llvm.org/D10781

llvm-svn: 241537
2015-07-07 02:08:46 +00:00

38 lines
722 B
YAML

# RUN: not llc -march=x86-64 -start-after branch-folder -stop-after branch-folder -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i32 @foo(i32* %p) {
entry:
%a = load i32, i32* %p
%b = icmp sle i32 %a, 10
br i1 %b, label %yes, label %nah
yes:
ret i32 0
nah:
ret i32 %a
}
...
---
name: foo
body:
- id: 0
name: entry
instructions:
- '%eax = MOV32rm %rdi, 1, _, 0, _'
- 'CMP32ri8 %eax, 10, implicit-def %eflags'
# CHECK: [[@LINE+1]]:18: expected a number after '%bb.'
- 'JG_1 %bb.nah, implicit %eflags'
- id: 1
name: yes
instructions:
- '%eax = MOV32r0 implicit-def %eflags'
- id: 2
name: nah
instructions:
- 'RETQ %eax'
...