1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 20:43:44 +02:00
llvm-mirror/test/CodeGen/MIR/X86/expected-subregister-after-colon.mir
Alex Lorenz cddac3ca8f MIR Serialization: Serialize the sub register indices.
This commit serializes the sub register indices from the register machine
operands.

Reviewers: Duncan P. N. Exon Smith
llvm-svn: 242084
2015-07-13 23:24:34 +00:00

30 lines
633 B
YAML

# RUN: not llc -march=x86-64 -start-after machine-sink -stop-after machine-sink -o /dev/null %s 2>&1 | FileCheck %s
--- |
define zeroext i1 @t(i1 %c) {
entry:
ret i1 %c
}
...
---
name: t
isSSA: true
tracksRegLiveness: true
registers:
- { id: 0, class: gr32 }
- { id: 1, class: gr8 }
- { id: 2, class: gr8 }
body:
- name: entry
id: 0
instructions:
- '%0 = COPY %edi'
# CHECK: [[@LINE+1]]:25: expected a subregister index after ':'
- '%1 = COPY %0 : 42'
- '%2 = AND8ri %1, 1, implicit-def %eflags'
- '%al = COPY %2'
- 'RETQ %al'
...