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c28d8cf19b
This commit removes the artificial types <512 x i1> and <1024 x i1>
from HVX intrinsics, and makes v512i1 and v1024i1 no longer legal on
Hexagon.
It may cause existing bitcode files to become invalid.
* Converting between vector predicates and vector registers must be
done explicitly via vandvrt/vandqrt instructions (their intrinsics),
i.e. (for 64-byte mode):
%Q = call <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %V, i32 -1)
%V = call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %Q, i32 -1)
The conversion intrinsics are:
declare <64 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32)
declare <128 x i1> @llvm.hexagon.V6.vandvrt.128B(<32 x i32>, i32)
declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32)
declare <32 x i32> @llvm.hexagon.V6.vandqrt.128B(<128 x i1>, i32)
They are all pure.
* Vector predicate values cannot be loaded/stored directly. This directly
reflects the architecture restriction. Loading and storing or vector
predicates must be done indirectly via vector registers and explicit
conversions via vandvrt/vandqrt instructions.
37 lines
1.6 KiB
LLVM
37 lines
1.6 KiB
LLVM
; RUN: llc -march=hexagon -O2 < %s
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; REQUIRES: asserts
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define inreg <16 x i32> @f0(i32 %a0, <16 x i32>* nocapture %a1) #0 {
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b0:
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%v0 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %a0)
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%v1 = tail call <64 x i1> @llvm.hexagon.V6.pred.not(<64 x i1> %v0)
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%v2 = icmp ult i32 %a0, 48
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br i1 %v2, label %b1, label %b2
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b1: ; preds = %b0
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%v3 = add nuw nsw i32 %a0, 16
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%v4 = tail call <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32 %v3)
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%v5 = tail call <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1> %v4, <64 x i1> %v1)
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br label %b2
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b2: ; preds = %b1, %b0
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%v6 = phi <64 x i1> [ %v5, %b1 ], [ %v1, %b0 ]
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%v7 = tail call <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1> %v6, i32 -1)
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%v8 = getelementptr inbounds <16 x i32>, <16 x i32>* %a1, i32 1
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%v9 = load <16 x i32>, <16 x i32>* %v8, align 64
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%v10 = getelementptr inbounds <16 x i32>, <16 x i32>* %a1, i32 2
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%v11 = load <16 x i32>, <16 x i32>* %v10, align 64
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%v12 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1> %v6, <16 x i32> %v9, <16 x i32> %v11)
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store <16 x i32> %v12, <16 x i32>* %a1, align 64
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ret <16 x i32> %v7
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}
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declare <16 x i32> @llvm.hexagon.V6.vandqrt(<64 x i1>, i32) #1
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declare <64 x i1> @llvm.hexagon.V6.pred.not(<64 x i1>) #1
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declare <64 x i1> @llvm.hexagon.V6.pred.scalar2(i32) #1
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declare <64 x i1> @llvm.hexagon.V6.pred.and(<64 x i1>, <64 x i1>) #1
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declare <16 x i32> @llvm.hexagon.V6.vmux(<64 x i1>, <16 x i32>, <16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
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attributes #1 = { nounwind readnone }
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