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d4c615be8c
Discussed here: http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html In preparation for adding support for named vregs we are changing the sigil for physical registers in MIR to '$' from '%'. This will prevent name clashes of named physical register with named vregs. llvm-svn: 323922
53 lines
1.8 KiB
YAML
53 lines
1.8 KiB
YAML
# RUN: llc -o - %s -mtriple=powerpc64le--linux-gnu -run-pass=branch-folder | FileCheck %s
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# The branch-folder should merge bb.1 and bb.5 below and therefore recalculate
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# the liveins list of the merged block. This test is checking whether this
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# recalculated list if okay and contains all the non-saved and saved CSRs.
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# CHECK-LABEL: name: func
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# CHECK: bb.3:
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# CHECK-NEXT: liveins: $x30, $x29, $x3, $x6
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# CHECK: $x4 = RLDICR killed $x6, 16, 47
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# CHECK: $x3 = OR8 killed $x4, killed $x3
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# CHECK: BLR8 implicit $lr8, implicit $rm, implicit $x3
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---
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name: func
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tracksRegLiveness: true
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fixedStack:
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- { id: 0, type: spill-slot, offset: -16, size: 8, alignment: 16, callee-saved-register: '$x30' }
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- { id: 1, type: spill-slot, offset: -24, size: 8, alignment: 8, callee-saved-register: '$x29' }
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- { id: 2, offset: -8, size: 8, alignment: 8, isImmutable: true, isAliased: false }
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body: |
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bb.0:
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liveins: $x3, $x5, $x29, $x30
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$x6 = RLWINM8 $x3, 16, 16, 31
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$x3 = RLDICL killed $x3, 0, 48
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BC undef $cr5lt, %bb.3
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bb.1:
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liveins: $x3, $x6, $x29, $x30
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$x4 = RLDICR killed $x6, 16, 47
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$x3 = OR8 killed $x4, killed $x3
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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bb.3:
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liveins: $x3, $x5, $x6, $x29, $x30
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dead $x5 = ADD8 $x5, $x6
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BC undef $cr5lt, %bb.1
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bb.6:
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liveins: $x3, $x6, $x29, $x30
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STD killed $x29, -24, $x1 :: (store 8 into %fixed-stack.1)
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STD killed $x30, -16, $x1 :: (store 8 into %fixed-stack.0, align 16)
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NOP implicit-def dead $x29
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NOP implicit-def dead $x30
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$x30 = LD -16, $x1 :: (load 8 from %fixed-stack.0, align 16)
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$x29 = LD -24, $x1 :: (load 8 from %fixed-stack.1)
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$x4 = RLDICR killed $x6, 16, 47
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$x3 = OR8 killed $x4, killed $x3
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BLR8 implicit $lr8, implicit $rm, implicit $x3
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...
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