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a50063c53c
This patch adds support for the RISC-V hard float ABIs, building on top of rL355771, which added basic target-abi parsing and MC layer support. It also builds on some re-organisations and expansion of the upstream ABI and calling convention tests which were recently committed directly upstream. A number of aspects of the RISC-V float hard float ABIs require frontend support (e.g. flattening of structs and passing int+fp for fp+fp structs in a pair of registers), and will be addressed in a Clang patch. As can be seen from the tests, it would be worthwhile extending RISCVMergeBaseOffsets to handle constant pool as well as global accesses. Differential Revision: https://reviews.llvm.org/D59357 llvm-svn: 357352
69 lines
2.1 KiB
LLVM
69 lines
2.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; RUN: llc -mtriple=riscv64 -mattr=+f -target-abi lp64f \
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; RUN: -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64I %s
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; This file contains tests that should have identical output for the lp64 and
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; lp64f ABIs. It doesn't check codegen when frame pointer elimination is
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; disabled, as there is sufficient coverage for this case in other files.
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define i64 @callee_double_in_regs(i64 %a, double %b) nounwind {
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; RV64I-LABEL: callee_double_in_regs:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: sd s0, 0(sp)
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; RV64I-NEXT: mv s0, a0
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; RV64I-NEXT: mv a0, a1
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; RV64I-NEXT: call __fixdfdi
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; RV64I-NEXT: add a0, s0, a0
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; RV64I-NEXT: ld s0, 0(sp)
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%b_fptosi = fptosi double %b to i64
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%1 = add i64 %a, %b_fptosi
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ret i64 %1
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}
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define i64 @caller_double_in_regs() nounwind {
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; RV64I-LABEL: caller_double_in_regs:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: addi a0, zero, 1
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; RV64I-NEXT: slli a1, a0, 62
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; RV64I-NEXT: addi a0, zero, 1
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; RV64I-NEXT: call callee_double_in_regs
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call i64 @callee_double_in_regs(i64 1, double 2.0)
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ret i64 %1
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}
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define double @callee_double_ret() nounwind {
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; RV64I-LABEL: callee_double_ret:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi a0, zero, 1023
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; RV64I-NEXT: slli a0, a0, 52
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; RV64I-NEXT: ret
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ret double 1.0
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}
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define i64 @caller_double_ret() nounwind {
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; RV64I-LABEL: caller_double_ret:
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; RV64I: # %bb.0:
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; RV64I-NEXT: addi sp, sp, -16
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; RV64I-NEXT: sd ra, 8(sp)
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; RV64I-NEXT: call callee_double_ret
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; RV64I-NEXT: ld ra, 8(sp)
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; RV64I-NEXT: addi sp, sp, 16
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; RV64I-NEXT: ret
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%1 = call double @callee_double_ret()
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%2 = bitcast double %1 to i64
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ret i64 %2
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}
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