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c55d376d9d
The MVE_VLDRWU32_qi_pre gather loads, like the other _pre/_post mve loads returns the writeback as result 0, the value as result 1. The llvm ir intrinsic seems to have this the other way around though, and so when lowering from one to the other we need to switch the first two outputs. I've also fixed up the types of _pre/_post on normal MVE loads. There we were already getting the values the right way around, just not for the types. I don't believe this was causing anything to go wrong, but it was very confusing to read in the debug output. Differential Revision: https://reviews.llvm.org/D73370
63 lines
2.6 KiB
LLVM
63 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve.fp -verify-machineinstrs -o - %s | FileCheck %s
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define arm_aapcs_vfpcc <4 x i32> @test_vldrwq_gather_base_wb_s32(<4 x i32>* %addr) {
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; CHECK-LABEL: test_vldrwq_gather_base_wb_s32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: vldrw.u32 q0, [q1, #80]!
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; CHECK-NEXT: vstrw.32 q1, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%0 = load <4 x i32>, <4 x i32>* %addr, align 8
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%1 = tail call { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32> %0, i32 80)
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%2 = extractvalue { <4 x i32>, <4 x i32> } %1, 1
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store <4 x i32> %2, <4 x i32>* %addr, align 8
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%3 = extractvalue { <4 x i32>, <4 x i32> } %1, 0
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ret <4 x i32> %3
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}
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declare { <4 x i32>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4i32.v4i32(<4 x i32>, i32)
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define arm_aapcs_vfpcc <4 x float> @test_vldrwq_gather_base_wb_f32(<4 x i32>* %addr) {
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; CHECK-LABEL: test_vldrwq_gather_base_wb_f32:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: vldrw.u32 q0, [q1, #64]!
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; CHECK-NEXT: vstrw.32 q1, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%0 = load <4 x i32>, <4 x i32>* %addr, align 8
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%1 = tail call { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32> %0, i32 64)
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%2 = extractvalue { <4 x float>, <4 x i32> } %1, 1
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store <4 x i32> %2, <4 x i32>* %addr, align 8
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%3 = extractvalue { <4 x float>, <4 x i32> } %1, 0
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ret <4 x float> %3
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}
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declare { <4 x float>, <4 x i32> } @llvm.arm.mve.vldr.gather.base.wb.v4f32.v4i32(<4 x i32>, i32)
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define arm_aapcs_vfpcc <2 x i64> @test_vldrdq_gather_base_wb_z_u64(<2 x i64>* %addr, i16 zeroext %p) {
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; CHECK-LABEL: test_vldrdq_gather_base_wb_z_u64:
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; CHECK: @ %bb.0: @ %entry
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; CHECK-NEXT: vmsr p0, r1
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; CHECK-NEXT: vldrw.u32 q1, [r0]
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; CHECK-NEXT: vpst
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; CHECK-NEXT: vldrdt.u64 q0, [q1, #656]!
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; CHECK-NEXT: vstrw.32 q1, [r0]
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; CHECK-NEXT: bx lr
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entry:
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%0 = load <2 x i64>, <2 x i64>* %addr, align 8
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%1 = zext i16 %p to i32
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%2 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %1)
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%3 = tail call { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v4i1(<2 x i64> %0, i32 656, <4 x i1> %2)
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%4 = extractvalue { <2 x i64>, <2 x i64> } %3, 1
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store <2 x i64> %4, <2 x i64>* %addr, align 8
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%5 = extractvalue { <2 x i64>, <2 x i64> } %3, 0
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ret <2 x i64> %5
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}
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declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
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declare { <2 x i64>, <2 x i64> } @llvm.arm.mve.vldr.gather.base.wb.predicated.v2i64.v2i64.v4i1(<2 x i64>, i32, <4 x i1>)
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