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https://github.com/RPCS3/llvm-mirror.git
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d09b64fc25
Adds an instruction itinerary to all x86 instructions, giving each a default latency of 1, using the InstrItinClass IIC_DEFAULT. Sets specific latencies for Atom for the instructions in files X86InstrCMovSetCC.td, X86InstrArithmetic.td, X86InstrControl.td, and X86InstrShiftRotate.td. The Atom latencies for the remainder of the x86 instructions will be set in subsequent patches. Adds a test to verify that the scheduler is working. Also changes the scheduling preference to "Hybrid" for i386 Atom, while leaving x86_64 as ILP. Patch by Preston Gurd! llvm-svn: 149558
54 lines
1.4 KiB
LLVM
54 lines
1.4 KiB
LLVM
; RUN: llc < %s -mcpu=generic -mtriple=x86_64-pc-win32 | FileCheck %s
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; Verify that the var arg parameters which are passed in registers are stored
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; in home stack slots allocated by the caller and that AP is correctly
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; calculated.
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define void @average_va(i32 %count, ...) nounwind {
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entry:
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; CHECK: pushq
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; CHECK: movq %r9, 40(%rsp)
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; CHECK: movq %r8, 32(%rsp)
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; CHECK: movq %rdx, 24(%rsp)
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; CHECK: leaq 24(%rsp), %rax
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%ap = alloca i8*, align 8 ; <i8**> [#uses=1]
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%ap1 = bitcast i8** %ap to i8* ; <i8*> [#uses=1]
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call void @llvm.va_start(i8* %ap1)
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ret void
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}
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declare void @llvm.va_start(i8*) nounwind
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; CHECK: f5:
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; CHECK: pushq
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; CHECK: leaq 56(%rsp),
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define i8* @f5(i64 %a0, i64 %a1, i64 %a2, i64 %a3, i64 %a4, ...) nounwind {
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entry:
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%ap = alloca i8*, align 8
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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ret i8* %ap1
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}
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; CHECK: f4:
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; CHECK: pushq
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; CHECK: leaq 48(%rsp),
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define i8* @f4(i64 %a0, i64 %a1, i64 %a2, i64 %a3, ...) nounwind {
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entry:
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%ap = alloca i8*, align 8
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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ret i8* %ap1
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}
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; CHECK: f3:
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; CHECK: pushq
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; CHECK: leaq 40(%rsp),
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define i8* @f3(i64 %a0, i64 %a1, i64 %a2, ...) nounwind {
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entry:
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%ap = alloca i8*, align 8
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%ap1 = bitcast i8** %ap to i8*
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call void @llvm.va_start(i8* %ap1)
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ret i8* %ap1
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}
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