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llvm-mirror/test/MC/Mips/mips64r5
Simon Dardis 449c500357 [mips] Fix c.<cc>.<fmt> instruction definition.
As part of this effort, remove MipsFCmp nodes and use tablegen
patterns rather than custom lowering through C++.

Unexpectedly, this improves codesize for microMIPS as previous floating
point setcc expansions would materialize 0 and 1 into GPRs before using
the relevant mov[tf].[sd] instruction. Now $zero is used directly.

Reviewers: dsanders, vkalintiris, zoran.jovanovic

Differential Review: https://reviews.llvm.org/D23118

llvm-svn: 281022
2016-09-09 09:22:52 +00:00
..
abi-bad.s [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
abiflags.s [mips] Don't derive the default ABI from the CPU in the backend. 2016-06-23 12:42:53 +00:00
invalid-mips64.s
invalid-mips64r2.s
invalid-mips64r3.s
invalid.s [mips][microMIPS] Implement LDC1, SDC1, LDC2, SDC2, LWC1, SWC1, LWC2 and SWC2 instructions and add CodeGen support 2016-07-11 07:41:56 +00:00
valid-xfail.s [mips] Fix c.<cc>.<fmt> instruction definition. 2016-09-09 09:22:52 +00:00
valid.s [mips] Fix c.<cc>.<fmt> instruction definition. 2016-09-09 09:22:52 +00:00