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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 11:13:28 +01:00
llvm-mirror/lib/Target/RISCV
2020-08-03 10:24:30 +08:00
..
AsmParser Upgrade MC to v0.9. 2020-08-01 07:42:06 +08:00
Disassembler
MCTargetDesc Upgrade MC to v0.9. 2020-08-01 07:42:06 +08:00
TargetInfo
Utils
CMakeLists.txt
LLVMBuild.txt
RISCV.h
RISCV.td [RISCV] Add support for -mcpu option. 2020-07-16 11:46:22 -07:00
RISCVAsmPrinter.cpp
RISCVCallingConv.td
RISCVCallLowering.cpp
RISCVCallLowering.h
RISCVExpandAtomicPseudoInsts.cpp [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos 2020-07-15 10:50:55 +01:00
RISCVExpandPseudoInsts.cpp [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos 2020-07-15 10:50:55 +01:00
RISCVFrameLowering.cpp
RISCVFrameLowering.h
RISCVInstrFormats.td Upgrade MC to v0.9. 2020-08-01 07:42:06 +08:00
RISCVInstrFormatsC.td
RISCVInstrFormatsV.td Upgrade MC to v0.9. 2020-08-01 07:42:06 +08:00
RISCVInstrInfo.cpp [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos 2020-07-15 10:50:55 +01:00
RISCVInstrInfo.h Upgrade MC to v0.9. 2020-08-01 07:42:06 +08:00
RISCVInstrInfo.td
RISCVInstrInfoA.td RISCV: Avoid GlobalISel build break in a future patch 2020-07-13 14:01:57 -04:00
RISCVInstrInfoB.td [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions 2020-07-15 12:19:34 +01:00
RISCVInstrInfoC.td
RISCVInstrInfoD.td
RISCVInstrInfoF.td
RISCVInstrInfoM.td
RISCVInstrInfoV.td Upgrade MC to v0.9. 2020-08-01 07:42:06 +08:00
RISCVInstructionSelector.cpp RISCV: Avoid GlobalISel build break in a future patch 2020-07-13 14:01:57 -04:00
RISCVISelDAGToDAG.cpp [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions 2020-07-15 12:19:34 +01:00
RISCVISelDAGToDAG.h [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions 2020-07-15 12:19:34 +01:00
RISCVISelLowering.cpp [RISCV] eliminate the repetition declare of SDLoc DL 2020-08-03 10:24:30 +08:00
RISCVISelLowering.h [RISCV] Optimize multiplication by constant 2020-07-07 18:50:24 -07:00
RISCVLegalizerInfo.cpp
RISCVLegalizerInfo.h
RISCVMachineFunctionInfo.h
RISCVMCInstLower.cpp Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo" 2020-07-14 11:15:01 +01:00
RISCVMergeBaseOffset.cpp
RISCVRegisterBankInfo.cpp
RISCVRegisterBankInfo.h
RISCVRegisterBanks.td
RISCVRegisterInfo.cpp
RISCVRegisterInfo.h
RISCVRegisterInfo.td
RISCVSchedRocket32.td
RISCVSchedRocket64.td
RISCVSchedule.td
RISCVSubtarget.cpp
RISCVSubtarget.h [RISCV] Refactor FeatureRVCHints to make ProcessorModel more intuitive 2020-07-09 23:07:39 -07:00
RISCVSystemOperands.td
RISCVTargetMachine.cpp Revert "[RISCV] Avoid Splitting MBB in RISCVExpandPseudo" 2020-07-14 11:15:01 +01:00
RISCVTargetMachine.h
RISCVTargetObjectFile.cpp
RISCVTargetObjectFile.h
RISCVTargetTransformInfo.cpp
RISCVTargetTransformInfo.h