Sander de Smalen 63fb4fcb81 [AArch64][SVE] Asm: Add SVE System registers ... This patch adds system registers for controlling aspects of SVE: - ZCR_EL1 (r/w) visible at EL1 and EL0. - ZCR_EL2 (r/w) visible at EL2 and Non-secure EL1 and EL0. - ZCR_EL3 (r/w) visible at all exception levels. and a system register identifying SVE: - ID_AA64ZFR0_EL1 (r) SVE Feature identifier. Reviewers: SjoerdMeijer, samparker, pbarrio, fhahn, javed.absar Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D50885 llvm-svn: 340158		2018-08-20 09:16:59 +00:00
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AArch64	[AArch64][SVE] Asm: Add SVE System registers	2018-08-20 09:16:59 +00:00
AMDGPU	[AMDGPU] Fix lit failures introduced in r335281	2018-06-21 22:30:09 +00:00
ARM	[ARM/AArch64] Support FP16 +fp16fml instructions	2018-08-17 11:29:49 +00:00
AsmParser	[AsmParser] Fix preserve-comments-crlf.s on FreeBSD	2018-07-26 06:07:03 +00:00
AVR
BPF
COFF	[MC] Improve COFF associative section lookup	2018-08-16 21:34:41 +00:00
Disassembler	[ARM/AArch64] Support FP16 +fp16fml instructions	2018-08-17 11:29:49 +00:00
ELF	[DWARF] Unclamp line table version on Darwin for v5 and later.	2018-08-08 21:16:50 +00:00
Hexagon	Check for tied operands	2018-08-13 14:01:25 +00:00
Lanai
MachO	[MC] Error on a .zerofill directive in a non-virtual section	2018-07-02 17:29:43 +00:00
Mips	[mips] Replace custom parsing logic for data directives by the addAliasForDirective	2018-07-25 07:07:43 +00:00
PowerPC	Complete the SPE instruction set patterns	2018-07-18 04:24:57 +00:00
RISCV	[RISC-V] Fixed alias for addi x2, x2, 0	2018-08-09 20:51:53 +00:00
Sparc	[Sparc] Add support for 13-bit PIC	2018-06-11 05:50:08 +00:00
SystemZ
WebAssembly	Revert "[WebAssembly] Added default stack-only instruction mode for MC."	2018-08-13 23:12:49 +00:00
X86	[MC][X86] Enhance X86 Register expression handling to more closely match GCC.	2018-08-16 16:31:14 +00:00