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44fc35bb88
llvm-mirror/lib/Target/AArch64
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Evandro Menezes 44fc35bb88 Add support to optionally limit the size of jump tables. 
Many high-performance processors have a dedicated branch predictor for
indirect branches, commonly used with jump tables.  As sophisticated as such
branch predictors are, they tend to have well defined limits beyond which
their effectiveness is hampered or even nullified.  One such limit is the
number of possible destinations for a given indirect branches that such
branch predictors can handle.

This patch considers a limit that a target may set to the number of
destination addresses in a jump table.

Patch by: Evandro Menezes <e.menezes@samsung.com>, Aditya Kumar
<aditya.k7@samsung.com>, Sebastian Pop <s.pop@samsung.com>.

Differential revision: https://reviews.llvm.org/D21940

llvm-svn: 282412
2016-09-26 15:32:33 +00:00
..
AsmParser Defer asm errors to post-statement failure 2016-09-16 18:30:20 +00:00
Disassembler Replace "fallthrough" comments with LLVM_FALLTHROUGH 2016-08-17 05:10:15 +00:00
InstPrinter
MCTargetDesc Revert "AArch64: Set shift bit of TLSLE HI12 add instruction" 2016-09-21 08:24:41 +00:00
TargetInfo
Utils AArch64: try to fix optimized build failure. 2016-07-05 23:15:58 +00:00
AArch64.h [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64.td Revert part of "AArch64: Do not test for CPUs, use SubtargetFeatures" 2016-09-20 19:02:09 +00:00
AArch64A53Fix835769.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
AArch64A57FPLoadBalancing.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
AArch64AddressTypePromotion.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64AdvSIMDScalarPass.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64AsmPrinter.cpp Use abstraction in AArch64AsmPrinter::lowerSTACKMAP. NFCI 2016-08-31 12:43:49 +00:00
AArch64BranchRelaxation.cpp Finish renaming remaining analyzeBranch functions 2016-09-14 20:43:16 +00:00
AArch64CallingConvention.h
AArch64CallingConvention.td GlobalISel: produce correct code for signext/zeroext ABI flags. 2016-09-21 12:57:45 +00:00
AArch64CallLowering.cpp GlobalISel: handle stack-based parameters on AArch64. 2016-09-22 13:49:25 +00:00
AArch64CallLowering.h GlobalISel: handle stack-based parameters on AArch64. 2016-09-22 13:49:25 +00:00
AArch64CleanupLocalDynamicTLSPass.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64CollectLOH.cpp Replace incorrect "#ifdef DEBUG" with "#ifndef NDEBUG". 2016-08-30 03:16:16 +00:00
AArch64ConditionalCompares.cpp Finish renaming remaining analyzeBranch functions 2016-09-14 20:43:16 +00:00
AArch64ConditionOptimizer.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64DeadRegisterDefinitionsPass.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
AArch64ExpandPseudoInsts.cpp [AArch64] Register AArch64LoadStoreOptimizer so it can be run by llc -run-pass. NFCI. 2016-07-20 21:45:58 +00:00
AArch64FastISel.cpp Swift Calling Convetion: add support for AArch64. 2016-08-26 19:28:17 +00:00
AArch64FrameLowering.cpp Move helpers into anonymous namespaces. NFC. 2016-08-06 11:13:10 +00:00
AArch64FrameLowering.h
AArch64GenRegisterBankInfo.def [AArch64][RegisterBankInfo] Switch to TableGen'ed like PartialMapping. 2016-09-23 00:14:36 +00:00
AArch64InstrAtomics.td AArch64: properly calculate cmpxchg status in FastISel. 2016-08-02 20:22:36 +00:00
AArch64InstrFormats.td [SelectionDAG] Rename fextend -> fpextend, fround -> fpround, frnd -> fround 2016-08-18 20:08:15 +00:00
AArch64InstrInfo.cpp [AArch64] Support for FP FMA when -ffp-contract=fast 2016-09-15 19:55:23 +00:00
AArch64InstrInfo.h Finish renaming remaining analyzeBranch functions 2016-09-14 20:43:16 +00:00
AArch64InstrInfo.td Revert "[AArch64] Use the reciprocal estimation machinery" 2016-09-20 19:02:06 +00:00
AArch64InstructionSelector.cpp GlobalISel: remove "unsized" LLT 2016-09-15 10:09:59 +00:00
AArch64InstructionSelector.h [GlobalISel] Introduce an instruction selector. 2016-07-27 14:31:55 +00:00
AArch64ISelDAGToDAG.cpp getValueType().getSizeInBits() -> getValueSizeInBits() ; NFCI 2016-09-14 16:05:51 +00:00
AArch64ISelLowering.cpp Add support to optionally limit the size of jump tables. 2016-09-26 15:32:33 +00:00
AArch64ISelLowering.h Revert "[AArch64] Use the reciprocal estimation machinery" 2016-09-20 19:02:06 +00:00
AArch64LoadStoreOptimizer.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
AArch64MachineFunctionInfo.h [AArch64] Mark various *Info classes as 'final'. NFC. 2016-07-27 14:31:46 +00:00
AArch64MachineLegalizer.cpp GlobalISel: legalize GEP instructions with small offsets. 2016-09-15 11:02:19 +00:00
AArch64MachineLegalizer.h Fix include case. NFC. 2016-07-22 20:15:19 +00:00
AArch64MCInstLower.cpp
AArch64MCInstLower.h
AArch64PBQPRegAlloc.cpp
AArch64PBQPRegAlloc.h
AArch64PerfectShuffle.h
AArch64PromoteConstant.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64RedundantCopyElimination.cpp MachineFunctionProperties/MIRParser: Rename AllVRegsAllocated->NoVRegs, compute it 2016-08-25 01:27:13 +00:00
AArch64RegisterBankInfo.cpp [RegisterBankInfo] Uniquely generate ValueMapping. 2016-09-24 04:53:52 +00:00
AArch64RegisterBankInfo.h [RegisterBankInfo] Move to statically allocated RegisterBank. 2016-09-22 02:10:37 +00:00
AArch64RegisterInfo.cpp MachineFunction: Return reference for getFrameInfo(); NFC 2016-07-28 18:40:00 +00:00
AArch64RegisterInfo.h [AArch64] Mark various *Info classes as 'final'. NFC. 2016-07-27 14:31:46 +00:00
AArch64RegisterInfo.td
AArch64SchedA53.td
AArch64SchedA57.td
AArch64SchedA57WriteRes.td
AArch64SchedCyclone.td
AArch64SchedKryo.td
AArch64SchedKryoDetails.td
AArch64SchedM1.td [AArch64] Adjust the scheduling model for Exynos M1. 2016-09-06 19:22:29 +00:00
AArch64Schedule.td
AArch64SchedVulcan.td
AArch64SelectionDAGInfo.cpp
AArch64SelectionDAGInfo.h
AArch64StorePairSuppress.cpp [AArch64] Register passes so they can be run by llc 2016-08-01 05:56:57 +00:00
AArch64Subtarget.cpp Add support to optionally limit the size of jump tables. 2016-09-26 15:32:33 +00:00
AArch64Subtarget.h Add support to optionally limit the size of jump tables. 2016-09-26 15:32:33 +00:00
AArch64SystemOperands.td
AArch64TargetMachine.cpp Revert "[AArch64] Use the reciprocal estimation machinery" 2016-09-20 19:02:06 +00:00
AArch64TargetMachine.h Revert "[AArch64] Use the reciprocal estimation machinery" 2016-09-20 19:02:06 +00:00
AArch64TargetObjectFile.cpp Move the Mangler from the AsmPrinter down to TLOF and clean up the 2016-09-16 07:33:15 +00:00
AArch64TargetObjectFile.h Move the Mangler from the AsmPrinter down to TLOF and clean up the 2016-09-16 07:33:15 +00:00
AArch64TargetTransformInfo.cpp
AArch64TargetTransformInfo.h
CMakeLists.txt [GlobalISel] Introduce an instruction selector. 2016-07-27 14:31:55 +00:00
LLVMBuild.txt