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05675977c5
This CPU definition is redundant. The Cortex-A9 is defined as supporting multiprocessing extensions. Remove its definition and update appropriate tests. LLVM defines both a cortex-a9 CPU and a cortex-a9-mp CPU. The only difference between the two CPU definitions in ARM.td is that cortex-a9-mp contains the feature FeatureMP for multiprocessing extensions. This is redundant since the Cortex-A9 is defined as having multiprocessing extensions in the TRMs. armcc also defines the Cortex-A9 as having multiprocessing extensions by default. Change-Id: Ifcadaa6c322be0a33d9d2a39cfdd7da1d75981a7 llvm-svn: 221166
87 lines
2.5 KiB
ArmAsm
87 lines
2.5 KiB
ArmAsm
@ RUN: llvm-mc -mcpu=cortex-a8 -triple arm-unknown-unknown -show-encoding %s \
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@ RUN: | FileCheck %s -check-prefix=ALL
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@ RUN: llvm-mc -mcpu=cortex-a9 -triple armv7-unknown-nacl -show-encoding %s \
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@ RUN: | FileCheck %s -check-prefix=NACL
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@ RUN: llvm-mc -mcpu=cortex-a8 -mattr=+nacl-trap -triple armv7 -show-encoding %s \
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@ RUN: | FileCheck %s -check-prefix=NACL
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@ ALL: trap
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@ ALL: encoding: [0xfe,0xde,0xff,0xe7]
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@ NACL: trap
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@ NACL: encoding: [0xf0,0xde,0xfe,0xe7]
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trap
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@ CHECK: bx lr
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@ CHECK: encoding: [0x1e,0xff,0x2f,0xe1]
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bx lr
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@ CHECK: vqdmull.s32 q8, d17, d16
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@ CHECK: encoding: [0xa0,0x0d,0xe1,0xf2]
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vqdmull.s32 q8, d17, d16
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@ CHECK: and r1, r2, r3 @ encoding: [0x03,0x10,0x02,0xe0]
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and r1,r2,r3
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@ CHECK: ands r1, r2, r3 @ encoding: [0x03,0x10,0x12,0xe0]
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ands r1,r2,r3
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@ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
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eor r1,r2,r3
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@ CHECK: eors r1, r2, r3 @ encoding: [0x03,0x10,0x32,0xe0]
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eors r1,r2,r3
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@ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
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sub r1,r2,r3
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@ CHECK: subs r1, r2, r3 @ encoding: [0x03,0x10,0x52,0xe0]
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subs r1,r2,r3
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@ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0]
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add r1,r2,r3
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@ CHECK: adds r1, r2, r3 @ encoding: [0x03,0x10,0x92,0xe0]
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adds r1,r2,r3
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@ CHECK: adc r1, r2, r3 @ encoding: [0x03,0x10,0xa2,0xe0]
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adc r1,r2,r3
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@ CHECK: bic r1, r2, r3 @ encoding: [0x03,0x10,0xc2,0xe1]
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bic r1,r2,r3
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@ CHECK: bics r1, r2, r3 @ encoding: [0x03,0x10,0xd2,0xe1]
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bics r1,r2,r3
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@ CHECK: mov r1, r2 @ encoding: [0x02,0x10,0xa0,0xe1]
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mov r1,r2
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@ CHECK: mvn r1, r2 @ encoding: [0x02,0x10,0xe0,0xe1]
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mvn r1,r2
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@ CHECK: mvns r1, r2 @ encoding: [0x02,0x10,0xf0,0xe1]
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mvns r1,r2
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@ CHECK: bfi r0, r0, #5, #7 @ encoding: [0x90,0x02,0xcb,0xe7]
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bfi r0, r0, #5, #7
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@ CHECK: bkpt #10 @ encoding: [0x7a,0x00,0x20,0xe1]
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bkpt #10
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@ CHECK: cdp p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xee]
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cdp p7, #1, c1, c1, c1, #4
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@ CHECK: cdp2 p7, #1, c1, c1, c1, #4 @ encoding: [0x81,0x17,0x11,0xfe]
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cdp2 p7, #1, c1, c1, c1, #4
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@ CHECK: add r1, r2, r3, lsl r4 @ encoding: [0x13,0x14,0x82,0xe0]
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add r1, r2, r3, lsl r4
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@ CHECK: ssat16 r0, #7, r0 @ encoding: [0x30,0x0f,0xa6,0xe6]
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ssat16 r0, #7, r0
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@ CHECK: cpsie none, #0 @ encoding: [0x00,0x00,0x0a,0xf1]
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cpsie none, #0
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@ CHECK: strh r3, [r2, #-0] @ encoding: [0xb0,0x30,0x42,0xe1]
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strh r3, [r2, #-0]
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