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78 lines
2.3 KiB
LLVM
78 lines
2.3 KiB
LLVM
;RUN: llc -mtriple=armv7-apple-darwin -show-mc-encoding < %s | FileCheck %s
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;FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
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; should run on .s source files rather than using llc to generate the
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; assembly.
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define i32 @foo(i32 %a, i32 %b) nounwind ssp {
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entry:
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; CHECK: foo
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; CHECK: trap @ encoding: [0xf0,0x00,0xf0,0x07]
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; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
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tail call void @llvm.trap()
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ret i32 undef
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}
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define i32 @f2(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK: f2
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; CHECK: add r0, r1, r0 @ encoding: [0x00,0x00,0x81,0xe0]
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; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
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%add = add nsw i32 %b, %a
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ret i32 %add
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}
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define i32 @f3(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK: f3
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; CHECK: add r0, r0, r1, lsl #3 @ encoding: [0x81,0x01,0x80,0xe0]
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; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
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%mul = shl i32 %b, 3
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%add = add nsw i32 %mul, %a
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ret i32 %add
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}
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define i32 @f4(i32 %a, i32 %b) nounwind readnone ssp {
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entry:
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; CHECK: f4
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; CHECK: add r0, r0, #254, 28 @ encoding: [0xfe,0x0e,0x80,0xe2]
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; CHECK: @ 4064
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; CHECK: bx lr @ encoding: [0x1e,0xff,0x2f,0xe1]
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%add = add nsw i32 %a, 4064
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ret i32 %add
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}
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define i32 @f5(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
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entry:
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; CHECK: f5
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; CHECK: cmp r0, r1 @ encoding: [0x01,0x00,0x50,0xe1]
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; CHECK: mov r0, r2 @ encoding: [0x02,0x00,0xa0,0xe1]
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; CHECK: movgt r0, r1 @ encoding: [0x01,0x00,0xa0,0xc1]
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%cmp = icmp sgt i32 %a, %b
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%retval.0 = select i1 %cmp, i32 %b, i32 %c
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ret i32 %retval.0
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}
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define i64 @f6(i64 %a, i64 %b, i64 %c) nounwind readnone optsize ssp {
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entry:
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; CHECK: f6
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; CHECK: adds r0, r2, r0 @ encoding: [0x00,0x00,0x92,0xe0]
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; CHECK: adc r1, r3, r1 @ encoding: [0x01,0x10,0xa3,0xe0]
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%add = add nsw i64 %b, %a
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ret i64 %add
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}
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define i32 @f7(i32 %a, i32 %b) nounwind readnone optsize ssp {
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entry:
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; CHECK: f7
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; CHECK: uxtab r0, r0, r1 @ encoding: [0x71,0x00,0xe0,0xe6]
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%and = and i32 %b, 255
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%add = add i32 %and, %a
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ret i32 %add
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}
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declare void @llvm.trap() nounwind
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