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https://github.com/RPCS3/llvm-mirror.git
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259 lines
6.3 KiB
LLVM
259 lines
6.3 KiB
LLVM
;RUN: llc -mtriple=armv7-apple-darwin -mcpu=cortex-a8 -mattr=-neonfp -show-mc-encoding < %s | FileCheck %s
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; FIXME: Once the ARM integrated assembler is up and going, these sorts of tests
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; should run on .s source files rather than using llc to generate the
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; assembly.
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define double @f1(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f1
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; CHECK: vadd.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x71,0xee]
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%add = fadd double %a, %b
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ret double %add
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}
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define float @f2(float %a, float %b) nounwind readnone {
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entry:
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; CHECK: f2
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; CHECK: vadd.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x30,0xee]
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%add = fadd float %a, %b
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ret float %add
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}
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define double @f3(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f3
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; CHECK: vsub.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x71,0xee]
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%sub = fsub double %a, %b
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ret double %sub
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}
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define float @f4(float %a, float %b) nounwind readnone {
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entry:
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; CHECK: f4
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; CHECK: vsub.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x30,0xee]
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%sub = fsub float %a, %b
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ret float %sub
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}
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define double @f5(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f5
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; CHECK: vdiv.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0xc1,0xee]
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%div = fdiv double %a, %b
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ret double %div
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}
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define float @f6(float %a, float %b) nounwind readnone {
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entry:
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; CHECK: f6
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; CHECK: vdiv.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x80,0xee]
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%div = fdiv float %a, %b
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ret float %div
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}
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define double @f7(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f7
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; CHECK: vmul.f64 d16, d17, d16 @ encoding: [0xa0,0x0b,0x61,0xee]
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%mul = fmul double %a, %b
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ret double %mul
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}
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define float @f8(float %a, float %b) nounwind readnone {
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entry:
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; CHECK: f8
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; CHECK: vmul.f32 s0, s1, s0 @ encoding: [0x80,0x0a,0x20,0xee]
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%mul = fmul float %a, %b
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ret float %mul
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}
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define double @f9(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f9
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; CHECK: vnmul.f64 d16, d17, d16 @ encoding: [0xe0,0x0b,0x61,0xee]
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%mul = fmul double %a, %b
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%sub = fsub double -0.000000e+00, %mul
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ret double %sub
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}
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define void @f10(float %a, float %b, float* %c) nounwind readnone {
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entry:
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; CHECK: f10
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; CHECK: vnmul.f32 s0, s1, s0 @ encoding: [0xc0,0x0a,0x20,0xee]
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%mul = fmul float %a, %b
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%sub = fsub float -0.000000e+00, %mul
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store float %sub, float* %c, align 4
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ret void
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}
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define i1 @f11(double %a, double %b) nounwind readnone {
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entry:
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; CHECK: f11
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; CHECK: vcmpe.f64 d17, d16 @ encoding: [0xe0,0x1b,0xf4,0xee]
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%cmp = fcmp oeq double %a, %b
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ret i1 %cmp
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}
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define i1 @f12(float %a, float %b) nounwind readnone {
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entry:
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; CHECK: f12
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; CHECK: vcmpe.f32 s1, s0 @ encoding: [0xc0,0x0a,0xf4,0xee]
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%cmp = fcmp oeq float %a, %b
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ret i1 %cmp
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}
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define i1 @f13(double %a) nounwind readnone {
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entry:
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; CHECK: f13
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; CHECK: vcmpe.f64 d16, #0 @ encoding: [0xc0,0x0b,0xf5,0xee]
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%cmp = fcmp oeq double %a, 0.000000e+00
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ret i1 %cmp
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}
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define i1 @f14(float %a) nounwind readnone {
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entry:
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; CHECK: f14
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; CHECK: vcmpe.f32 s0, #0 @ encoding: [0xc0,0x0a,0xb5,0xee]
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%cmp = fcmp oeq float %a, 0.000000e+00
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ret i1 %cmp
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}
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define double @f15(double %a) nounwind {
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entry:
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; CHECK: f15
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; CHECK: vabs.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf0,0xee]
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%call = tail call double @fabsl(double %a)
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ret double %call
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}
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declare double @fabsl(double)
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define float @f16(float %a) nounwind {
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entry:
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; CHECK: f16
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; FIXME: This call generates a "bfc" instruction instead of "vabs.f32".
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%call = tail call float @fabsf(float %a)
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ret float %call
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}
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declare float @fabsf(float)
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define float @f17(double %a) nounwind readnone {
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entry:
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; CHECK: f17
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; CHECK: vcvt.f32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xb7,0xee]
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%conv = fptrunc double %a to float
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ret float %conv
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}
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define double @f18(float %a) nounwind readnone {
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entry:
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; CHECK: f18
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; CHECK: vcvt.f64.f32 d16, s0 @ encoding: [0xc0,0x0a,0xf7,0xee]
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%conv = fpext float %a to double
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ret double %conv
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}
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define double @f19(double %a) nounwind readnone {
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entry:
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; CHECK: f19
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; CHECK: vneg.f64 d16, d16 @ encoding: [0x60,0x0b,0xf1,0xee]
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%sub = fsub double -0.000000e+00, %a
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ret double %sub
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}
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define float @f20(float %a) nounwind readnone {
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entry:
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; CHECK: f20
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; FIXME: This produces an 'eor' instruction.
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%sub = fsub float -0.000000e+00, %a
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ret float %sub
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}
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define double @f21(double %a) nounwind readnone {
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entry:
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; CHECK: f21
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; CHECK: vsqrt.f64 d16, d16 @ encoding: [0xe0,0x0b,0xf1,0xee]
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%call = tail call double @sqrtl(double %a) nounwind
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ret double %call
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}
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declare double @sqrtl(double) readnone
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define float @f22(float %a) nounwind readnone {
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entry:
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; CHECK: f22
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; CHECK: vsqrt.f32 s0, s0 @ encoding: [0xc0,0x0a,0xb1,0xee]
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%call = tail call float @sqrtf(float %a) nounwind
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ret float %call
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}
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declare float @sqrtf(float) readnone
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define double @f23(i32 %a) nounwind readnone {
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entry:
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; CHECK: f23
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; CHECK: vcvt.f64.s32 d16, s0 @ encoding: [0xc0,0x0b,0xf8,0xee]
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%conv = sitofp i32 %a to double
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ret double %conv
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}
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define float @f24(i32 %a) nounwind readnone {
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entry:
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; CHECK: f24
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; CHECK: vcvt.f32.s32 s0, s0 @ encoding: [0xc0,0x0a,0xb8,0xee]
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%conv = sitofp i32 %a to float
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ret float %conv
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}
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define double @f25(i32 %a) nounwind readnone {
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entry:
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; CHECK: f25
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; CHECK: vcvt.f64.u32 d16, s0 @ encoding: [0x40,0x0b,0xf8,0xee]
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%conv = uitofp i32 %a to double
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ret double %conv
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}
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define float @f26(i32 %a) nounwind readnone {
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entry:
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; CHECK: f26
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; CHECK: vcvt.f32.u32 s0, s0 @ encoding: [0x40,0x0a,0xb8,0xee]
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%conv = uitofp i32 %a to float
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ret float %conv
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}
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define i32 @f27(double %a) nounwind readnone {
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entry:
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; CHECK: f27
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; CHECK: vcvt.s32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbd,0xee]
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%conv = fptosi double %a to i32
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ret i32 %conv
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}
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define i32 @f28(float %a) nounwind readnone {
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entry:
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; CHECK: f28
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; CHECK: vcvt.s32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbd,0xee]
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%conv = fptosi float %a to i32
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ret i32 %conv
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}
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define i32 @f29(double %a) nounwind readnone {
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entry:
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; CHECK: f29
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; CHECK: vcvt.u32.f64 s0, d16 @ encoding: [0xe0,0x0b,0xbc,0xee]
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%conv = fptoui double %a to i32
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ret i32 %conv
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}
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define i32 @f30(float %a) nounwind readnone {
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entry:
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; CHECK: f30
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; CHECK: vcvt.u32.f32 s0, s0 @ encoding: [0xc0,0x0a,0xbc,0xee]
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%conv = fptoui float %a to i32
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ret i32 %conv
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}
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