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llvm-mirror/test/CodeGen
2015-06-15 21:52:13 +00:00
..
AArch64 On behalf of Alexandros Lamprineas: 2015-06-15 15:48:44 +00:00
AMDGPU R600 -> AMDGPU rename 2015-06-13 03:28:10 +00:00
ARM [ARM] Disabling vfp4 should disable fp16 2015-06-12 09:38:51 +00:00
BPF [bpf] rename triple names bpf_be -> bpfeb 2015-06-05 16:11:14 +00:00
CPP
Generic
Hexagon [Hexagon] PC-relative offsets are relative to packet start rather than the offset of the relocation. Set relocation addend and check it's correct in the ELF. 2015-06-15 21:52:13 +00:00
Inputs
Mips [mips] Make TTypeEncoding indirect to allow .eh_frame to be read-only. 2015-06-02 20:32:50 +00:00
MIR MIR Serialization: Connect the machine function analysis pass to the MIR parser. 2015-06-15 20:30:22 +00:00
MSP430
NVPTX [NVPTX] fix a crash bug in NVPTXFavorNonGenericAddrSpaces 2015-06-09 21:50:32 +00:00
PowerPC LLVM support for vector quad bit permute and gather instructions through builtins 2015-06-11 06:21:25 +00:00
SPARC
SystemZ
Thumb Revert r238473, "Thumb2: Modify codegen for memcpy intrinsic to prefer LDM/STM." 2015-06-05 18:01:28 +00:00
Thumb2 ARM: Thumb2 LDRD/STRD supports independent input/output regs 2015-06-03 16:30:24 +00:00
WinEH
X86 [X86][SSE] Added tests for vector i8/i16 to f32/f64 conversions 2015-06-15 21:49:31 +00:00
XCore