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abbe59490b
* Fix spacing, grammar in comment * Make code layout consistent * Wrap code at 80 cols * Delete spurious blank lines No functional changes. llvm-svn: 14721
486 lines
15 KiB
C++
486 lines
15 KiB
C++
//===-- MachineInstr.cpp --------------------------------------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// Methods common to all machine instructions.
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//
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// FIXME: Now that MachineInstrs have parent pointers, they should always
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// print themselves using their MachineFunction's TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/Value.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/MRegisterInfo.h"
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#include "Support/LeakDetector.h"
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#include <iostream>
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using namespace llvm;
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// Global variable holding an array of descriptors for machine instructions.
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// The actual object needs to be created separately for each target machine.
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// This variable is initialized and reset by class TargetInstrInfo.
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//
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// FIXME: This should be a property of the target so that more than one target
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// at a time can be active...
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//
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namespace llvm {
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extern const TargetInstrDescriptor *TargetInstrDescriptors;
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}
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// Constructor for instructions with variable #operands
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MachineInstr::MachineInstr(short opcode, unsigned numOperands)
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: Opcode(opcode),
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numImplicitRefs(0),
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operands(numOperands, MachineOperand()),
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parent(0) {
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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}
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/// MachineInstr ctor - This constructor only does a _reserve_ of the operands,
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/// not a resize for them. It is expected that if you use this that you call
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/// add* methods below to fill up the operands, instead of the Set methods.
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/// Eventually, the "resizing" ctors will be phased out.
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///
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MachineInstr::MachineInstr(short opcode, unsigned numOperands, bool XX, bool YY)
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: Opcode(opcode), numImplicitRefs(0), parent(0) {
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operands.reserve(numOperands);
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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}
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/// MachineInstr ctor - Work exactly the same as the ctor above, except that the
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/// MachineInstr is created and added to the end of the specified basic block.
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///
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MachineInstr::MachineInstr(MachineBasicBlock *MBB, short opcode,
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unsigned numOperands)
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: Opcode(opcode), numImplicitRefs(0), parent(0) {
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assert(MBB && "Cannot use inserting ctor with null basic block!");
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operands.reserve(numOperands);
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// Make sure that we get added to a machine basicblock
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LeakDetector::addGarbageObject(this);
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MBB->push_back(this); // Add instruction to end of basic block!
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}
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/// MachineInstr ctor - Copies MachineInstr arg exactly
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///
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MachineInstr::MachineInstr(const MachineInstr &MI) {
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Opcode = MI.getOpcode();
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numImplicitRefs = MI.getNumImplicitRefs();
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operands.reserve(MI.getNumOperands());
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// Add operands
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for (unsigned i = 0; i < MI.getNumOperands(); ++i)
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operands.push_back(MachineOperand(MI.getOperand(i)));
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// Set parent, next, and prev to null
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parent = 0;
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prev = 0;
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next = 0;
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}
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MachineInstr::~MachineInstr() {
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LeakDetector::removeGarbageObject(this);
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}
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/// clone - Create a copy of 'this' instruction that is identical in all ways
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/// except the following: the new instruction has no parent and it has no name
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///
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MachineInstr* MachineInstr::clone() const {
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return new MachineInstr(*this);
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}
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/// OperandComplete - Return true if it's illegal to add a new operand
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///
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bool MachineInstr::OperandsComplete() const {
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int NumOperands = TargetInstrDescriptors[Opcode].numOperands;
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if (NumOperands >= 0 && getNumOperands() >= (unsigned)NumOperands)
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return true; // Broken: we have all the operands of this instruction!
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return false;
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}
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/// replace - Support for replacing opcode and operands of a MachineInstr in
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/// place. This only resets the size of the operand vector and initializes it.
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/// The new operands must be set explicitly later.
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///
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void MachineInstr::replace(short opcode, unsigned numOperands) {
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assert(getNumImplicitRefs() == 0 &&
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"This is probably broken because implicit refs are going to be lost.");
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Opcode = opcode;
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operands.clear();
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operands.resize(numOperands, MachineOperand());
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}
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void MachineInstr::SetMachineOperandVal(unsigned i,
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MachineOperand::MachineOperandType opTy,
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Value* V) {
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assert(i < operands.size()); // may be explicit or implicit op
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operands[i].opType = opTy;
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operands[i].contents.value = V;
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operands[i].regNum = -1;
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}
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void
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MachineInstr::SetMachineOperandConst(unsigned i,
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MachineOperand::MachineOperandType opTy,
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int intValue) {
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assert(i < getNumOperands()); // must be explicit op
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assert(TargetInstrDescriptors[Opcode].resultPos != (int) i &&
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"immed. constant cannot be defined");
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operands[i].opType = opTy;
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operands[i].contents.value = NULL;
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operands[i].contents.immedVal = intValue;
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operands[i].regNum = -1;
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operands[i].flags = 0;
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}
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void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
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assert(i < getNumOperands()); // must be explicit op
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operands[i].opType = MachineOperand::MO_MachineRegister;
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operands[i].contents.value = NULL;
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operands[i].regNum = regNum;
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}
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// Used only by the SPARC back-end.
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void MachineInstr::SetRegForOperand(unsigned i, int regNum) {
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assert(i < getNumOperands()); // must be explicit op
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operands[i].setRegForValue(regNum);
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}
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// Used only by the SPARC back-end.
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void MachineInstr::SetRegForImplicitRef(unsigned i, int regNum) {
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getImplicitOp(i).setRegForValue(regNum);
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}
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/// substituteValue - Substitute all occurrences of Value* oldVal with newVal
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/// in all operands and all implicit refs. If defsOnly == true, substitute defs
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/// only.
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///
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/// FIXME: Fold this into its single caller, at SparcInstrSelection.cpp:2865,
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/// or make it a static function in that file.
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///
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unsigned
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MachineInstr::substituteValue(const Value* oldVal, Value* newVal,
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bool defsOnly, bool notDefsAndUses,
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bool& someArgsWereIgnored)
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{
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assert((!defsOnly || !notDefsAndUses) &&
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"notDefsAndUses is irrelevant if defsOnly == true.");
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unsigned numSubst = 0;
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// Substitute operands
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for (MachineInstr::val_op_iterator O = begin(), E = end(); O != E; ++O)
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if (*O == oldVal)
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if (!defsOnly ||
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notDefsAndUses && (O.isDef() && !O.isUse()) ||
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!notDefsAndUses && O.isDef())
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{
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O.getMachineOperand().contents.value = newVal;
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++numSubst;
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} else
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someArgsWereIgnored = true;
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// Substitute implicit refs
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for (unsigned i = 0, N = getNumImplicitRefs(); i < N; ++i)
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if (getImplicitRef(i) == oldVal) {
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MachineOperand Op = getImplicitOp(i);
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if (!defsOnly ||
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notDefsAndUses && (Op.isDef() && !Op.isUse()) ||
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!notDefsAndUses && Op.isDef())
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{
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Op.contents.value = newVal;
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++numSubst;
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} else
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someArgsWereIgnored = true;
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}
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return numSubst;
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}
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void MachineInstr::dump() const {
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std::cerr << " " << *this;
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}
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static inline std::ostream& OutputValue(std::ostream &os, const Value* val) {
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os << "(val ";
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os << (void*) val; // print address always
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if (val && val->hasName())
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os << " " << val->getName(); // print name also, if available
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os << ")";
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return os;
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}
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static inline void OutputReg(std::ostream &os, unsigned RegNo,
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const MRegisterInfo *MRI = 0) {
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if (!RegNo || MRegisterInfo::isPhysicalRegister(RegNo)) {
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if (MRI)
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os << "%" << MRI->get(RegNo).Name;
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else
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os << "%mreg(" << RegNo << ")";
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} else
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os << "%reg" << RegNo;
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}
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static void print(const MachineOperand &MO, std::ostream &OS,
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const TargetMachine *TM) {
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const MRegisterInfo *MRI = 0;
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if (TM) MRI = TM->getRegisterInfo();
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bool CloseParen = true;
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if (MO.isHiBits32())
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OS << "%lm(";
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else if (MO.isLoBits32())
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OS << "%lo(";
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else if (MO.isHiBits64())
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OS << "%hh(";
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else if (MO.isLoBits64())
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OS << "%hm(";
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else
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CloseParen = false;
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (MO.getVRegValue()) {
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OS << "%reg";
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OutputValue(OS, MO.getVRegValue());
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if (MO.hasAllocatedReg())
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OS << "==";
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}
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if (MO.hasAllocatedReg())
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OutputReg(OS, MO.getReg(), MRI);
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break;
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case MachineOperand::MO_CCRegister:
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OS << "%ccreg";
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OutputValue(OS, MO.getVRegValue());
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if (MO.hasAllocatedReg()) {
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OS << "==";
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OutputReg(OS, MO.getReg(), MRI);
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}
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break;
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case MachineOperand::MO_MachineRegister:
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OutputReg(OS, MO.getMachineRegNum(), MRI);
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break;
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case MachineOperand::MO_SignExtendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_UnextendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_PCRelativeDisp: {
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const Value* opVal = MO.getVRegValue();
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bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
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OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
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if (opVal->hasName())
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OS << opVal->getName();
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else
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OS << (const void*) opVal;
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OS << ")";
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break;
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}
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case MachineOperand::MO_MachineBasicBlock:
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OS << "mbb<"
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<< ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
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<< "," << (void*)MO.getMachineBasicBlock() << ">";
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break;
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case MachineOperand::MO_FrameIndex:
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OS << "<fi#" << MO.getFrameIndex() << ">";
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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OS << "<cp#" << MO.getConstantPoolIndex() << ">";
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break;
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case MachineOperand::MO_GlobalAddress:
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OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
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break;
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case MachineOperand::MO_ExternalSymbol:
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OS << "<es:" << MO.getSymbolName() << ">";
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break;
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default:
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assert(0 && "Unrecognized operand type");
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}
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if (CloseParen)
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OS << ")";
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}
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void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
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unsigned StartOp = 0;
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// Specialize printing if op#0 is definition
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if (getNumOperands() && getOperand(0).isDef() && !getOperand(0).isUse()) {
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::print(getOperand(0), OS, TM);
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OS << " = ";
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++StartOp; // Don't print this operand again!
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}
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// Must check if Target machine is not null because machine BB could not
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// be attached to a Machine function yet
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if (TM)
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OS << TM->getInstrInfo()->getName(getOpcode());
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for (unsigned i = StartOp, e = getNumOperands(); i != e; ++i) {
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const MachineOperand& mop = getOperand(i);
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if (i != StartOp)
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OS << ",";
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OS << " ";
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::print(mop, OS, TM);
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if (mop.isDef())
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if (mop.isUse())
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OS << "<def&use>";
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else
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OS << "<def>";
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}
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// code for printing implicit references
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if (getNumImplicitRefs()) {
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OS << "\tImplicitRefs: ";
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for (unsigned i = 0, e = getNumImplicitRefs(); i != e; ++i) {
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OS << "\t";
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OutputValue(OS, getImplicitRef(i));
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if (getImplicitOp(i).isDef())
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if (getImplicitOp(i).isUse())
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OS << "<def&use>";
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else
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OS << "<def>";
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}
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}
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OS << "\n";
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}
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namespace llvm {
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std::ostream &operator<<(std::ostream &os, const MachineInstr &MI) {
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// If the instruction is embedded into a basic block, we can find the target
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// info for the instruction.
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if (const MachineBasicBlock *MBB = MI.getParent()) {
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const MachineFunction *MF = MBB->getParent();
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if (MF)
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MI.print(os, &MF->getTarget());
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else
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MI.print(os, 0);
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return os;
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}
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// Otherwise, print it out in the "raw" format without symbolic register names
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// and such.
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os << TargetInstrDescriptors[MI.getOpcode()].Name;
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for (unsigned i = 0, N = MI.getNumOperands(); i < N; i++) {
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os << "\t" << MI.getOperand(i);
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if (MI.getOperand(i).isDef())
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if (MI.getOperand(i).isUse())
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os << "<d&u>";
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else
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os << "<d>";
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}
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// code for printing implicit references
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unsigned NumOfImpRefs = MI.getNumImplicitRefs();
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if (NumOfImpRefs > 0) {
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os << "\tImplicit: ";
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for (unsigned z = 0; z < NumOfImpRefs; z++) {
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OutputValue(os, MI.getImplicitRef(z));
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if (MI.getImplicitOp(z).isDef())
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if (MI.getImplicitOp(z).isUse())
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os << "<d&u>";
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else
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os << "<d>";
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os << "\t";
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}
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}
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return os << "\n";
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}
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std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
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if (MO.isHiBits32())
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OS << "%lm(";
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else if (MO.isLoBits32())
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OS << "%lo(";
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else if (MO.isHiBits64())
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OS << "%hh(";
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else if (MO.isLoBits64())
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OS << "%hm(";
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switch (MO.getType()) {
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case MachineOperand::MO_VirtualRegister:
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if (MO.hasAllocatedReg())
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OutputReg(OS, MO.getReg());
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if (MO.getVRegValue()) {
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if (MO.hasAllocatedReg()) OS << "==";
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OS << "%vreg";
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OutputValue(OS, MO.getVRegValue());
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}
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break;
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case MachineOperand::MO_CCRegister:
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OS << "%ccreg";
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OutputValue(OS, MO.getVRegValue());
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if (MO.hasAllocatedReg()) {
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OS << "==";
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OutputReg(OS, MO.getReg());
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}
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break;
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case MachineOperand::MO_MachineRegister:
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OutputReg(OS, MO.getMachineRegNum());
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break;
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case MachineOperand::MO_SignExtendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_UnextendedImmed:
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OS << (long)MO.getImmedValue();
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break;
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case MachineOperand::MO_PCRelativeDisp: {
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const Value* opVal = MO.getVRegValue();
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bool isLabel = isa<Function>(opVal) || isa<BasicBlock>(opVal);
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OS << "%disp(" << (isLabel? "label " : "addr-of-val ");
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if (opVal->hasName())
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OS << opVal->getName();
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else
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OS << (const void*) opVal;
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OS << ")";
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break;
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}
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case MachineOperand::MO_MachineBasicBlock:
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OS << "<mbb:"
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<< ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
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<< "@" << (void*)MO.getMachineBasicBlock() << ">";
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break;
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case MachineOperand::MO_FrameIndex:
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OS << "<fi#" << MO.getFrameIndex() << ">";
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break;
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case MachineOperand::MO_ConstantPoolIndex:
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OS << "<cp#" << MO.getConstantPoolIndex() << ">";
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break;
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case MachineOperand::MO_GlobalAddress:
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OS << "<ga:" << ((Value*)MO.getGlobal())->getName() << ">";
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break;
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case MachineOperand::MO_ExternalSymbol:
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OS << "<es:" << MO.getSymbolName() << ">";
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break;
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default:
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assert(0 && "Unrecognized operand type");
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break;
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}
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if (MO.isHiBits32() || MO.isLoBits32() || MO.isHiBits64() || MO.isLoBits64())
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OS << ")";
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return OS;
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}
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}
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