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fcede394cf
Transform: (store ch addr (add x (add (shl y c) e)))
to: (store ch addr (add x (shl (add y d) c))),
where e = (shl d c) for some integer d.
The purpose of this is to enable generation of loads/stores with
shifted addressing mode, i.e. mem(x+y<<#c). For that, the shift
value c must be 0, 1 or 2.
llvm-svn: 273466
51 lines
2.0 KiB
LLVM
51 lines
2.0 KiB
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; CHECK-DAG: r[[BASE:[0-9]+]] += add
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; CHECK-DAG: r[[IDX0:[0-9]+]] = add(r2, #5)
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; CHECK-DAG: r[[IDX1:[0-9]+]] = add(r2, #6)
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; CHECK-DAG: memw(r0 + r[[IDX0]]<<#2) = r3
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; CHECK-DAG: memw(r0 + r[[IDX1]]<<#2) = r3
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; CHECK-DAG: memw(r[[BASE]] + r[[IDX0]]<<#2) = r[[IDX0]]
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; CHECK-DAG: memw(r[[BASE]] + r[[IDX1]]<<#2) = r[[IDX0]]
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target triple = "hexagon"
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@G = external global i32, align 4
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; Function Attrs: norecurse nounwind
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define void @fred(i32* nocapture %A, [50 x i32]* nocapture %B, i32 %N, i32 %M) #0 {
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entry:
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%add = add nsw i32 %N, 5
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%arrayidx = getelementptr inbounds i32, i32* %A, i32 %add
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store i32 %M, i32* %arrayidx, align 4, !tbaa !1
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%add2 = add nsw i32 %N, 6
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%arrayidx3 = getelementptr inbounds i32, i32* %A, i32 %add2
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store i32 %M, i32* %arrayidx3, align 4, !tbaa !1
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%add4 = add nsw i32 %N, 35
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%arrayidx5 = getelementptr inbounds i32, i32* %A, i32 %add4
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store i32 %add, i32* %arrayidx5, align 4, !tbaa !1
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%arrayidx8 = getelementptr inbounds [50 x i32], [50 x i32]* %B, i32 %add, i32 %add
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store i32 %add, i32* %arrayidx8, align 4, !tbaa !1
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%inc = add nsw i32 %N, 6
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%arrayidx8.1 = getelementptr inbounds [50 x i32], [50 x i32]* %B, i32 %add, i32 %inc
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store i32 %add, i32* %arrayidx8.1, align 4, !tbaa !1
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%sub = add nsw i32 %N, 4
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%arrayidx10 = getelementptr inbounds [50 x i32], [50 x i32]* %B, i32 %add, i32 %sub
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%0 = load i32, i32* %arrayidx10, align 4, !tbaa !1
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%add11 = add nsw i32 %0, 1
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store i32 %add11, i32* %arrayidx10, align 4, !tbaa !1
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%1 = load i32, i32* %arrayidx, align 4, !tbaa !1
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%add13 = add nsw i32 %N, 25
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%arrayidx15 = getelementptr inbounds [50 x i32], [50 x i32]* %B, i32 %add13, i32 %add
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store i32 %1, i32* %arrayidx15, align 4, !tbaa !1
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store i32 5, i32* @G, align 4, !tbaa !1
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ret void
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}
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attributes #0 = { norecurse nounwind "target-cpu"="hexagonv60" "target-features"="+hvx,-hvx-double" }
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!1 = !{!2, !2, i64 0}
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!2 = !{!"int", !3, i64 0}
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!3 = !{!"omnipotent char", !4, i64 0}
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!4 = !{!"Simple C/C++ TBAA"}
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