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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-22 20:43:44 +02:00
llvm-mirror/test/CodeGen
Sanjay Patel 458e63ca85 [DAGCombiner] fold assertzexts separated by trunc
If we have an AssertZext of a truncated value that has already been AssertZext'ed, 
we can assert on the wider source op to improve the zext-y knowledge:
 assert (trunc (assert X, i8) to iN), i1 --> trunc (assert X, i1) to iN

This moves a fold from being Mips-specific to general combining, and x86 shows
improvements.

Differential Revision: https://reviews.llvm.org/D37017

llvm-svn: 313577
2017-09-18 22:05:35 +00:00
..
AArch64 [LoopVectorizer] Add more testcases for PR33804. 2017-09-18 17:28:15 +00:00
AMDGPU AMDGPU: Start selecting s_xnor_{b32, b64} 2017-09-18 21:22:45 +00:00
ARC
ARM [LoopVectorizer] Add more testcases for PR33804. 2017-09-18 17:28:15 +00:00
AVR
BPF
Generic
Hexagon [IfConversion] More simple, correct dead/kill liveness handling 2017-09-14 15:53:11 +00:00
Inputs
Lanai
Mips [mips] Pick the right variant of DINS upfront and enable target instruction verification 2017-09-14 10:58:00 +00:00
MIR
MSP430
Nios2
NVPTX
PowerPC [XRay][CodeGen] Use the current function symbol as the associated symbol for the instrumentation map 2017-09-14 07:08:23 +00:00
SPARC
SystemZ Move llvm/test/CodeGen/X86/clear-liverange-spillreg.mir to SystemZ. It was in wrong place. 2017-09-14 00:03:23 +00:00
Thumb
Thumb2
WebAssembly [WebAssembly] Add sign extend instructions from atomics proposal 2017-09-13 00:29:06 +00:00
WinEH
X86 [DAGCombiner] fold assertzexts separated by trunc 2017-09-18 22:05:35 +00:00
XCore