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702277f07f
Replace spills to memory with spills to registers, if possible. This applies mostly to predicate registers (both scalar and vector), since they are very limited in number. A spill of a predicate register may happen even if there is a general-purpose register available. In cases like this the stack spill/reload may be eliminated completely. This optimization will consider all stack objects, regardless of where they came from and try to match the live range of the stack slot with a dead range of a register from an appropriate register class. llvm-svn: 260758
81 lines
4.3 KiB
LLVM
81 lines
4.3 KiB
LLVM
; RUN: llc -march=hexagon -mcpu=hexagonv60 -O2 -enable-hexagon-hvx < %s | FileCheck %s
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; CHECK: vmem(r{{[0-9]+}}+#3) = v{{[0-9]+}}
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; CHECK: call puts
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; CHECK: call print_vecpred
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; CHECK: v{{[0-9]+}}{{ *}}={{ *}}vmem(r{{[0-9]+}}+#3)
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target triple = "hexagon"
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@K = global i64 0, align 8
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@src = global i32 -1, align 4
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@Q6VecPredResult = common global <16 x i32> zeroinitializer, align 64
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@dst_addresses = common global [15 x i64] zeroinitializer, align 8
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@ptr_addresses = common global [15 x i8*] zeroinitializer, align 8
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@src_addresses = common global [15 x i8*] zeroinitializer, align 8
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@ptr = common global [32768 x i32] zeroinitializer, align 8
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@vecpreds = common global [15 x <16 x i32>] zeroinitializer, align 64
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@VectorResult = common global <16 x i32> zeroinitializer, align 64
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@vectors = common global [15 x <16 x i32>] zeroinitializer, align 64
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@VectorPairResult = common global <32 x i32> zeroinitializer, align 128
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@vector_pairs = common global [15 x <32 x i32>] zeroinitializer, align 128
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@str = private unnamed_addr constant [106 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),INT32_MIN)\00"
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@str3 = private unnamed_addr constant [99 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),-1)\00"
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@str4 = private unnamed_addr constant [98 x i8] c"Q6VecPred4 : Q6_Q_vandor_QVR(Q6_Q_vand_VR(Q6_V_vsplat_R(1+1),(0x01010101)),Q6_V_vsplat_R(0+1),0)\00"
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; Function Attrs: nounwind
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define i32 @main() #0 {
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entry:
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%call = tail call i32 bitcast (i32 (...)* @init_addresses to i32 ()*)() #3
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%call1 = tail call i32 @acquire_vector_unit(i8 zeroext 0) #3
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tail call void @init_vectors() #3
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%0 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 2)
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%1 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32> %0, i32 16843009)
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%2 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 1)
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%3 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 -2147483648)
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%4 = bitcast <512 x i1> %3 to <16 x i32>
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store <16 x i32> %4, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1
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%puts = tail call i32 @puts(i8* getelementptr inbounds ([106 x i8], [106 x i8]* @str, i32 0, i32 0))
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tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3
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%5 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 -1)
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%6 = bitcast <512 x i1> %5 to <16 x i32>
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store <16 x i32> %6, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1
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%puts5 = tail call i32 @puts(i8* getelementptr inbounds ([99 x i8], [99 x i8]* @str3, i32 0, i32 0))
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tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3
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%7 = tail call <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1> %1, <16 x i32> %2, i32 0)
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%8 = bitcast <512 x i1> %7 to <16 x i32>
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store <16 x i32> %8, <16 x i32>* @Q6VecPredResult, align 64, !tbaa !1
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%puts6 = tail call i32 @puts(i8* getelementptr inbounds ([98 x i8], [98 x i8]* @str4, i32 0, i32 0))
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tail call void @print_vecpred(i32 512, i8* bitcast (<16 x i32>* @Q6VecPredResult to i8*)) #3
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ret i32 0
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}
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declare i32 @init_addresses(...) #1
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declare i32 @acquire_vector_unit(i8 zeroext) #1
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declare void @init_vectors() #1
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; Function Attrs: nounwind readnone
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declare <512 x i1> @llvm.hexagon.V6.vandvrt.acc(<512 x i1>, <16 x i32>, i32) #2
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; Function Attrs: nounwind readnone
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declare <512 x i1> @llvm.hexagon.V6.vandvrt(<16 x i32>, i32) #2
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #2
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declare void @print_vecpred(i32, i8*) #1
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; Function Attrs: nounwind
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declare i32 @puts(i8* nocapture readonly) #3
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attributes #0 = { nounwind "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #1 = { "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
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attributes #2 = { nounwind readnone }
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attributes #3 = { nounwind }
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!1 = !{!2, !2, i64 0}
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!2 = !{!"omnipotent char", !3, i64 0}
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!3 = !{!"Simple C/C++ TBAA"}
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