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064cc1a22c
This patch adds a pipeline to support in-order CPUs such as ARM Cortex-A55. In-order pipeline implements a simplified version of Dispatch, Scheduler and Execute stages as a single stage. Entry and Retire stages are common for both in-order and out-of-order pipelines. Differential Revision: https://reviews.llvm.org/D94928
48 lines
1.5 KiB
TableGen
48 lines
1.5 KiB
TableGen
// RUN: llvm-tblgen -gen-subtarget -I %p/../../include %s 2>&1 | FileCheck %s
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// Check if it is valid MCSchedClassDesc if didn't have the resources.
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include "llvm/Target/Target.td"
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def MyTarget : Target;
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let OutOperandList = (outs), InOperandList = (ins) in {
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def Inst_A : Instruction;
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def Inst_B : Instruction;
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}
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let CompleteModel = 0 in {
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def SchedModel_A: SchedMachineModel;
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def SchedModel_B: SchedMachineModel;
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def SchedModel_C: SchedMachineModel;
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}
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// Inst_B didn't have the resoures, and it is invalid.
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// CHECK: SchedModel_ASchedClasses[] = {
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// CHECK: {DBGFIELD("Inst_A") 1
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// CHECK-NEXT: {DBGFIELD("Inst_B") 8191
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let SchedModel = SchedModel_A in {
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def Write_A : SchedWriteRes<[]>;
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def : InstRW<[Write_A], (instrs Inst_A)>;
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}
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// Inst_A didn't have the resoures, and it is invalid.
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// CHECK: SchedModel_BSchedClasses[] = {
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// CHECK: {DBGFIELD("Inst_A") 8191
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// CHECK-NEXT: {DBGFIELD("Inst_B") 1
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let SchedModel = SchedModel_B in {
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def Write_B: SchedWriteRes<[]>;
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def : InstRW<[Write_B], (instrs Inst_B)>;
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}
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// CHECK: SchedModel_CSchedClasses[] = {
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// CHECK: {DBGFIELD("Inst_A") 1
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// CHECK-NEXT: {DBGFIELD("Inst_B") 1
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let SchedModel = SchedModel_C in {
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def Write_C: SchedWriteRes<[]>;
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def : InstRW<[Write_C], (instrs Inst_A, Inst_B)>;
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}
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def ProcessorA: ProcessorModel<"ProcessorA", SchedModel_A, []>;
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def ProcessorB: ProcessorModel<"ProcessorB", SchedModel_B, []>;
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def ProcessorC: ProcessorModel<"ProcessorC", SchedModel_C, []>;
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