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293 lines
11 KiB
TableGen
293 lines
11 KiB
TableGen
//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file describes the SparcV8 instructions in TableGen format.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Instruction format superclass
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//===----------------------------------------------------------------------===//
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class InstV8 : Instruction { // SparcV8 instruction baseline
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field bits<32> Inst;
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let Namespace = "V8";
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bits<2> op;
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let Inst{31-30} = op; // Top two bits are the 'op' field
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// Bit attributes specific to SparcV8 instructions
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bit isPasi = 0; // Does this instruction affect an alternate addr space?
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bit isPrivileged = 0; // Is this a privileged instruction?
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}
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include "SparcV8InstrFormats.td"
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//===----------------------------------------------------------------------===//
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// Instructions
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//===----------------------------------------------------------------------===//
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// Pseudo instructions.
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class PseudoInstV8<string nm> : InstV8 {
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let Name = nm;
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}
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def PHI : PseudoInstV8<"PHI">;
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def ADJCALLSTACKDOWN : PseudoInstV8<"ADJCALLSTACKDOWN">;
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def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP">;
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def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE">;
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def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF">;
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def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move
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// Section A.3 - Synthetic Instructions, p. 85
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// special cases of JMPL:
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let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
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let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
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def RET : F3_2<2, 0b111000, "ret">;
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let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
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def RETL: F3_2<2, 0b111000, "retl">;
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}
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// CMP is a special case of SUBCC where destination is ignored, by setting it to
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// %g0 (hardwired zero).
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// FIXME: should keep track of the fact that it defs the integer condition codes
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let rd = 0 in
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def CMPri: F3_2<2, 0b010100, "cmp">;
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// Section B.1 - Load Integer Instructions, p. 90
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def LDSB: F3_2<3, 0b001001, "ldsb">;
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def LDSH: F3_2<3, 0b001010, "ldsh">;
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def LDUB: F3_2<3, 0b000001, "ldub">;
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def LDUH: F3_2<3, 0b000010, "lduh">;
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def LD : F3_2<3, 0b000000, "ld">;
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def LDD : F3_2<3, 0b000011, "ldd">;
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// Section B.2 - Load Floating-point Instructions, p. 92
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def LDFrr : F3_1<3, 0b100000, "ld">;
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def LDFri : F3_2<3, 0b100000, "ld">;
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def LDDFrr : F3_1<3, 0b100011, "ldd">;
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def LDDFri : F3_2<3, 0b100011, "ldd">;
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def LDFSRrr: F3_1<3, 0b100001, "ld">;
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def LDFSRri: F3_2<3, 0b100001, "ld">;
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// Section B.4 - Store Integer Instructions, p. 95
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def STB : F3_2<3, 0b000101, "stb">;
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def STH : F3_2<3, 0b000110, "sth">;
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def ST : F3_2<3, 0b000100, "st">;
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def STD : F3_2<3, 0b000111, "std">;
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// Section B.5 - Store Floating-point Instructions, p. 97
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def STFrr : F3_1<3, 0b100100, "st">;
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def STFri : F3_2<3, 0b100100, "st">;
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def STDFrr : F3_1<3, 0b100111, "std">;
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def STDFri : F3_2<3, 0b100111, "std">;
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def STFSRrr : F3_1<3, 0b100101, "st">;
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def STFSRri : F3_2<3, 0b100101, "st">;
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def STDFQrr : F3_1<3, 0b100110, "std">;
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def STDFQri : F3_2<3, 0b100110, "std">;
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// Section B.9 - SETHI Instruction, p. 104
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def SETHIi: F2_1<0b100, "sethi">;
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// Section B.10 - NOP Instruction, p. 105
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// (It's a special case of SETHI)
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let rd = 0, imm22 = 0 in
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def NOP : F2_1<0b100, "nop">;
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// Section B.11 - Logical Instructions, p. 106
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def ANDrr : F3_1<2, 0b000001, "and">;
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def ANDri : F3_2<2, 0b000001, "and">;
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def ANDCCrr : F3_1<2, 0b010001, "andcc">;
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def ANDCCri : F3_2<2, 0b010001, "andcc">;
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def ANDNrr : F3_1<2, 0b000101, "andn">;
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def ANDNri : F3_2<2, 0b000101, "andn">;
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def ANDNCCrr: F3_1<2, 0b010101, "andncc">;
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def ANDNCCri: F3_2<2, 0b010101, "andncc">;
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def ORrr : F3_1<2, 0b000010, "or">;
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def ORri : F3_2<2, 0b000010, "or">;
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def ORCCrr : F3_1<2, 0b010010, "orcc">;
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def ORCCri : F3_2<2, 0b010010, "orcc">;
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def ORNrr : F3_1<2, 0b000110, "orn">;
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def ORNri : F3_2<2, 0b000110, "orn">;
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def ORNCCrr : F3_1<2, 0b010110, "orncc">;
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def ORNCCri : F3_2<2, 0b010110, "orncc">;
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def XORrr : F3_1<2, 0b000011, "xor">;
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def XORri : F3_2<2, 0b000011, "xor">;
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def XORCCrr : F3_1<2, 0b010011, "xorcc">;
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def XORCCri : F3_2<2, 0b010011, "xorcc">;
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def XNORrr : F3_1<2, 0b000111, "xnor">;
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def XNORri : F3_2<2, 0b000111, "xnor">;
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def XNORCCrr: F3_1<2, 0b010111, "xnorcc">;
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def XNORCCri: F3_2<2, 0b010111, "xnorcc">;
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// Section B.12 - Shift Instructions, p. 107
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def SLLrr : F3_1<2, 0b100101, "sll">;
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def SLLri : F3_2<2, 0b100101, "sll">;
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def SRLrr : F3_1<2, 0b100110, "srl">;
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def SRLri : F3_2<2, 0b100110, "srl">;
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def SRArr : F3_1<2, 0b100111, "sra">;
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def SRAri : F3_2<2, 0b100111, "sra">;
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// Section B.13 - Add Instructions, p. 108
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def ADDrr : F3_1<2, 0b000000, "add">;
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def ADDri : F3_2<2, 0b000000, "add">;
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def ADDCCrr : F3_1<2, 0b010000, "addcc">;
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def ADDCCri : F3_2<2, 0b010000, "addcc">;
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def ADDXrr : F3_1<2, 0b001000, "addx">;
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def ADDXri : F3_2<2, 0b001000, "addx">;
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def ADDXCCrr: F3_1<2, 0b011000, "addxcc">;
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def ADDXCCri: F3_2<2, 0b011000, "addxcc">;
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// Section B.15 - Subtract Instructions, p. 110
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def SUBrr : F3_1<2, 0b000100, "sub">;
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def SUBri : F3_2<2, 0b000100, "sub">;
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def SUBCCrr : F3_1<2, 0b010100, "subcc">;
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def SUBCCri : F3_2<2, 0b010100, "subcc">;
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def SUBXrr : F3_1<2, 0b001100, "subx">;
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def SUBXri : F3_2<2, 0b001100, "subx">;
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def SUBXCCrr: F3_1<2, 0b011100, "subxcc">;
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def SUBXCCri: F3_2<2, 0b011100, "subxcc">;
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// Section B.18 - Multiply Instructions, p. 113
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def UMULrr : F3_1<2, 0b001010, "umul">;
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def SMULrr : F3_1<2, 0b001011, "smul">;
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// Section B.19 - Divide Instructions, p. 115
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def UDIVrr : F3_1<2, 0b001110, "udiv">;
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def UDIVri : F3_2<2, 0b001110, "udiv">;
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def SDIVrr : F3_1<2, 0b001111, "sdiv">;
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def SDIVri : F3_2<2, 0b001111, "sdiv">;
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def UDIVCCrr : F3_1<2, 0b011110, "udivcc">;
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def UDIVCCri : F3_2<2, 0b011110, "udivcc">;
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def SDIVCCrr : F3_1<2, 0b011111, "sdivcc">;
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def SDIVCCri : F3_2<2, 0b011111, "sdivcc">;
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// Section B.20 - SAVE and RESTORE, p. 117
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def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
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def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
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def RESTORErr : F3_1<2, 0b111101, "restore">; // restore r, r, r
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def RESTOREri : F3_2<2, 0b111101, "restore">; // restore r, i, r
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// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
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// conditional branch class:
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class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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}
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let isBarrier = 1 in
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def BA : BranchV8<0b1000, "ba">;
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def BN : BranchV8<0b0000, "bn">;
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def BNE : BranchV8<0b1001, "bne">;
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def BE : BranchV8<0b0001, "be">;
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def BG : BranchV8<0b1010, "bg">;
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def BLE : BranchV8<0b0010, "ble">;
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def BGE : BranchV8<0b1011, "bge">;
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def BL : BranchV8<0b0011, "bl">;
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def BGU : BranchV8<0b1100, "bgu">;
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def BLEU : BranchV8<0b0100, "bleu">;
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def BCC : BranchV8<0b1101, "bcc">;
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def BCS : BranchV8<0b0101, "bcs">;
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// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
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// floating-point conditional branch class:
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class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> {
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let isBranch = 1;
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let isTerminator = 1;
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let hasDelaySlot = 1;
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}
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def FBA : FPBranchV8<0b1000, "fba">;
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def FBN : FPBranchV8<0b0000, "fbn">;
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def FBU : FPBranchV8<0b0111, "fbu">;
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def FBG : FPBranchV8<0b0110, "fbg">;
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def FBUG : FPBranchV8<0b0101, "fbug">;
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def FBL : FPBranchV8<0b0100, "fbl">;
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def FBUL : FPBranchV8<0b0011, "fbul">;
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def FBLG : FPBranchV8<0b0010, "fblg">;
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def FBNE : FPBranchV8<0b0001, "fbne">;
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def FBE : FPBranchV8<0b1001, "fbe">;
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def FBUE : FPBranchV8<0b1010, "fbue">;
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def FBGE : FPBranchV8<0b1011, "fbge">;
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def FBUGE: FPBranchV8<0b1100, "fbuge">;
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def FBLE : FPBranchV8<0b1101, "fble">;
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def FBULE: FPBranchV8<0b1110, "fbule">;
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def FBO : FPBranchV8<0b1111, "fbo">;
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// Section B.24 - Call and Link Instruction, p. 125
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// This is the only Format 1 instruction
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let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
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// pc-relative call:
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let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
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D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
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def CALL : InstV8 {
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bits<30> disp;
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let op = 1;
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let Inst{29-0} = disp;
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let Name = "call";
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}
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// indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
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// be an implicit def):
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let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
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D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
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def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
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}
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// Section B.29 - Write State Register Instructions
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def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
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def WRri : F3_2<2, 0b110000, "wr">; // wr rs1, imm, rd
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// Convert Integer to Floating-point Instructions, p. 141
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def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">;
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def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">;
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// Convert Floating-point to Integer Instructions, p. 142
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def FSTOI : F3_3<2, 0b110100, 0b011010001, "fstoi">;
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def FDTOI : F3_3<2, 0b110100, 0b011010010, "fdtoi">;
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// Convert between Floating-point Formats Instructions, p. 143
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def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">;
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def FDTOS : F3_3<2, 0b110100, 0b011000110, "fdtos">;
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// Floating-point Move Instructions, p. 144
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def FMOVS : F3_3<2, 0b110100, 0b000000001, "fmovs">;
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def FNEGS : F3_3<2, 0b110100, 0b000000101, "fnegs">;
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def FABSS : F3_3<2, 0b110100, 0b000001001, "fabss">;
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// Floating-point Add and Subtract Instructions, p. 146
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def FADDS : F3_3<2, 0b110100, 0b001000001, "fadds">;
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def FADDD : F3_3<2, 0b110100, 0b001000010, "faddd">;
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def FSUBS : F3_3<2, 0b110100, 0b001000101, "fsubs">;
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def FSUBD : F3_3<2, 0b110100, 0b001000110, "fsubd">;
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// Floating-point Multiply and Divide Instructions, p. 147
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def FMULS : F3_3<2, 0b110100, 0b001001001, "fmuls">;
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def FMULD : F3_3<2, 0b110100, 0b001001010, "fmuld">;
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def FSMULD : F3_3<2, 0b110100, 0b001101001, "fsmuld">;
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def FDIVS : F3_3<2, 0b110100, 0b001001101, "fdivs">;
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def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">;
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// Floating-point Compare Instructions, p. 148
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// Note: the 2nd template arg is different for these guys.
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// Note 2: the result of a FCMP is not available until the 2nd cycle
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// after the instr is retired, but there is no interlock. This behavior
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// is modelled as a delay slot.
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let hasDelaySlot = 1 in {
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def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">;
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def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
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def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
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def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;
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}
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