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285 lines
11 KiB
C++
285 lines
11 KiB
C++
//===-- X86SelectionDAGInfo.cpp - X86 SelectionDAG Info -------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the X86SelectionDAGInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "X86InstrInfo.h"
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#include "X86ISelLowering.h"
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#include "X86RegisterInfo.h"
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#include "X86Subtarget.h"
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#include "X86SelectionDAGInfo.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/Target/TargetLowering.h"
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using namespace llvm;
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#define DEBUG_TYPE "x86-selectiondag-info"
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bool X86SelectionDAGInfo::isBaseRegConflictPossible(
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SelectionDAG &DAG, ArrayRef<MCPhysReg> ClobberSet) const {
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// We cannot use TRI->hasBasePointer() until *after* we select all basic
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// blocks. Legalization may introduce new stack temporaries with large
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// alignment requirements. Fall back to generic code if there are any
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// dynamic stack adjustments (hopefully rare) and the base pointer would
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// conflict if we had to use it.
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MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
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if (!MFI->hasVarSizedObjects() && !MFI->hasOpaqueSPAdjustment())
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return false;
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const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>(
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DAG.getSubtarget().getRegisterInfo());
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unsigned BaseReg = TRI->getBaseRegister();
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for (unsigned R : ClobberSet)
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if (BaseReg == R)
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return true;
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return false;
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}
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SDValue X86SelectionDAGInfo::EmitTargetCodeForMemset(
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SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src,
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SDValue Size, unsigned Align, bool isVolatile,
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MachinePointerInfo DstPtrInfo) const {
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ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
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const X86Subtarget &Subtarget =
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DAG.getMachineFunction().getSubtarget<X86Subtarget>();
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#ifndef NDEBUG
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// If the base register might conflict with our physical registers, bail out.
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const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI,
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X86::ECX, X86::EAX, X86::EDI};
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assert(!isBaseRegConflictPossible(DAG, ClobberSet));
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#endif
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// If to a segment-relative address space, use the default lowering.
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if (DstPtrInfo.getAddrSpace() >= 256)
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return SDValue();
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// If not DWORD aligned or size is more than the threshold, call the library.
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// The libc version is likely to be faster for these cases. It can use the
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// address value and run time information about the CPU.
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if ((Align & 3) != 0 || !ConstantSize ||
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ConstantSize->getZExtValue() > Subtarget.getMaxInlineSizeThreshold()) {
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// Check to see if there is a specialized entry-point for memory zeroing.
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ConstantSDNode *V = dyn_cast<ConstantSDNode>(Src);
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if (const char *bzeroEntry = V &&
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V->isNullValue() ? Subtarget.getBZeroEntry() : nullptr) {
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const TargetLowering &TLI = DAG.getTargetLoweringInfo();
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EVT IntPtr = TLI.getPointerTy(DAG.getDataLayout());
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Type *IntPtrTy = DAG.getDataLayout().getIntPtrType(*DAG.getContext());
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TargetLowering::ArgListTy Args;
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TargetLowering::ArgListEntry Entry;
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Entry.Node = Dst;
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Entry.Ty = IntPtrTy;
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Args.push_back(Entry);
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Entry.Node = Size;
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Args.push_back(Entry);
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TargetLowering::CallLoweringInfo CLI(DAG);
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CLI.setDebugLoc(dl).setChain(Chain)
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.setCallee(CallingConv::C, Type::getVoidTy(*DAG.getContext()),
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DAG.getExternalSymbol(bzeroEntry, IntPtr), std::move(Args),
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0)
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.setDiscardResult();
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std::pair<SDValue,SDValue> CallResult = TLI.LowerCallTo(CLI);
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return CallResult.second;
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}
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// Otherwise have the target-independent code call memset.
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return SDValue();
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}
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uint64_t SizeVal = ConstantSize->getZExtValue();
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SDValue InFlag;
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EVT AVT;
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SDValue Count;
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ConstantSDNode *ValC = dyn_cast<ConstantSDNode>(Src);
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unsigned BytesLeft = 0;
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bool TwoRepStos = false;
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if (ValC) {
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unsigned ValReg;
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uint64_t Val = ValC->getZExtValue() & 255;
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// If the value is a constant, then we can potentially use larger sets.
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switch (Align & 3) {
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case 2: // WORD aligned
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AVT = MVT::i16;
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ValReg = X86::AX;
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Val = (Val << 8) | Val;
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break;
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case 0: // DWORD aligned
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AVT = MVT::i32;
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ValReg = X86::EAX;
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Val = (Val << 8) | Val;
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Val = (Val << 16) | Val;
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if (Subtarget.is64Bit() && ((Align & 0x7) == 0)) { // QWORD aligned
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AVT = MVT::i64;
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ValReg = X86::RAX;
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Val = (Val << 32) | Val;
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}
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break;
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default: // Byte aligned
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AVT = MVT::i8;
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ValReg = X86::AL;
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Count = DAG.getIntPtrConstant(SizeVal, dl);
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break;
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}
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if (AVT.bitsGT(MVT::i8)) {
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unsigned UBytes = AVT.getSizeInBits() / 8;
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Count = DAG.getIntPtrConstant(SizeVal / UBytes, dl);
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BytesLeft = SizeVal % UBytes;
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}
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Chain = DAG.getCopyToReg(Chain, dl, ValReg, DAG.getConstant(Val, dl, AVT),
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InFlag);
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InFlag = Chain.getValue(1);
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} else {
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AVT = MVT::i8;
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Count = DAG.getIntPtrConstant(SizeVal, dl);
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Chain = DAG.getCopyToReg(Chain, dl, X86::AL, Src, InFlag);
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InFlag = Chain.getValue(1);
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}
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Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX,
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Count, InFlag);
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InFlag = Chain.getValue(1);
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Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI,
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Dst, InFlag);
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InFlag = Chain.getValue(1);
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
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Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
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if (TwoRepStos) {
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InFlag = Chain.getValue(1);
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Count = Size;
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EVT CVT = Count.getValueType();
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SDValue Left = DAG.getNode(ISD::AND, dl, CVT, Count,
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DAG.getConstant((AVT == MVT::i64) ? 7 : 3, dl,
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CVT));
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Chain = DAG.getCopyToReg(Chain, dl, (CVT == MVT::i64) ? X86::RCX : X86::ECX,
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Left, InFlag);
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InFlag = Chain.getValue(1);
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Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = { Chain, DAG.getValueType(MVT::i8), InFlag };
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Chain = DAG.getNode(X86ISD::REP_STOS, dl, Tys, Ops);
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} else if (BytesLeft) {
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// Handle the last 1 - 7 bytes.
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unsigned Offset = SizeVal - BytesLeft;
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EVT AddrVT = Dst.getValueType();
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EVT SizeVT = Size.getValueType();
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Chain = DAG.getMemset(Chain, dl,
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DAG.getNode(ISD::ADD, dl, AddrVT, Dst,
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DAG.getConstant(Offset, dl, AddrVT)),
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Src,
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DAG.getConstant(BytesLeft, dl, SizeVT),
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Align, isVolatile, false,
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DstPtrInfo.getWithOffset(Offset));
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}
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// TODO: Use a Tokenfactor, as in memcpy, instead of a single chain.
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return Chain;
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}
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SDValue X86SelectionDAGInfo::EmitTargetCodeForMemcpy(
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SelectionDAG &DAG, SDLoc dl, SDValue Chain, SDValue Dst, SDValue Src,
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SDValue Size, unsigned Align, bool isVolatile, bool AlwaysInline,
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MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const {
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// This requires the copy size to be a constant, preferably
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// within a subtarget-specific limit.
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ConstantSDNode *ConstantSize = dyn_cast<ConstantSDNode>(Size);
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const X86Subtarget &Subtarget =
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DAG.getMachineFunction().getSubtarget<X86Subtarget>();
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if (!ConstantSize)
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return SDValue();
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uint64_t SizeVal = ConstantSize->getZExtValue();
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if (!AlwaysInline && SizeVal > Subtarget.getMaxInlineSizeThreshold())
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return SDValue();
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/// If not DWORD aligned, it is more efficient to call the library. However
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/// if calling the library is not allowed (AlwaysInline), then soldier on as
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/// the code generated here is better than the long load-store sequence we
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/// would otherwise get.
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if (!AlwaysInline && (Align & 3) != 0)
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return SDValue();
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// If to a segment-relative address space, use the default lowering.
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if (DstPtrInfo.getAddrSpace() >= 256 ||
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SrcPtrInfo.getAddrSpace() >= 256)
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return SDValue();
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// If the base register might conflict with our physical registers, bail out.
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const MCPhysReg ClobberSet[] = {X86::RCX, X86::RSI, X86::RDI,
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X86::ECX, X86::ESI, X86::EDI};
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if (isBaseRegConflictPossible(DAG, ClobberSet))
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return SDValue();
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MVT AVT;
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if (Align & 1)
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AVT = MVT::i8;
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else if (Align & 2)
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AVT = MVT::i16;
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else if (Align & 4)
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// DWORD aligned
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AVT = MVT::i32;
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else
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// QWORD aligned
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AVT = Subtarget.is64Bit() ? MVT::i64 : MVT::i32;
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unsigned UBytes = AVT.getSizeInBits() / 8;
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unsigned CountVal = SizeVal / UBytes;
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SDValue Count = DAG.getIntPtrConstant(CountVal, dl);
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unsigned BytesLeft = SizeVal % UBytes;
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SDValue InFlag;
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Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RCX : X86::ECX,
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Count, InFlag);
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InFlag = Chain.getValue(1);
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Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RDI : X86::EDI,
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Dst, InFlag);
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InFlag = Chain.getValue(1);
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Chain = DAG.getCopyToReg(Chain, dl, Subtarget.is64Bit() ? X86::RSI : X86::ESI,
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Src, InFlag);
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InFlag = Chain.getValue(1);
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SDVTList Tys = DAG.getVTList(MVT::Other, MVT::Glue);
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SDValue Ops[] = { Chain, DAG.getValueType(AVT), InFlag };
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SDValue RepMovs = DAG.getNode(X86ISD::REP_MOVS, dl, Tys, Ops);
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SmallVector<SDValue, 4> Results;
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Results.push_back(RepMovs);
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if (BytesLeft) {
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// Handle the last 1 - 7 bytes.
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unsigned Offset = SizeVal - BytesLeft;
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EVT DstVT = Dst.getValueType();
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EVT SrcVT = Src.getValueType();
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EVT SizeVT = Size.getValueType();
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Results.push_back(DAG.getMemcpy(Chain, dl,
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DAG.getNode(ISD::ADD, dl, DstVT, Dst,
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DAG.getConstant(Offset, dl,
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DstVT)),
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DAG.getNode(ISD::ADD, dl, SrcVT, Src,
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DAG.getConstant(Offset, dl,
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SrcVT)),
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DAG.getConstant(BytesLeft, dl, SizeVT),
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Align, isVolatile, AlwaysInline, false,
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DstPtrInfo.getWithOffset(Offset),
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SrcPtrInfo.getWithOffset(Offset)));
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}
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return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Results);
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}
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