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124f45603b
- Expand SELECT_CC and BR_CC for vector types. - Implement TLI::isShuffleMaskLegal. llvm-svn: 281397
22 lines
688 B
LLVM
22 lines
688 B
LLVM
; RUN: llc -march=hexagon < %s | FileCheck %s
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; Check that we don't crash.
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; CHECK: vshuff
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target triple = "hexagon"
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define void @hex_interleaved.s0.__outermost() local_unnamed_addr #0 {
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entry:
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%0 = icmp eq i32 undef, 0
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%sel2 = select i1 %0, <32 x i16> undef, <32 x i16> zeroinitializer
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%1 = bitcast <32 x i16> %sel2 to <16 x i32>
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%2 = tail call <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32> %1)
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store <16 x i32> %2, <16 x i32>* undef, align 2
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unreachable
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}
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; Function Attrs: nounwind readnone
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declare <16 x i32> @llvm.hexagon.V6.vshuffh(<16 x i32>) #1
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attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvx" }
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attributes #1 = { nounwind readnone }
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