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49 lines
1.5 KiB
LLVM
49 lines
1.5 KiB
LLVM
; RUN: llc -march=hexagon -relocation-model=pic < %s | FileCheck %s
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add({{pc|PC}}{{ *}},{{ *}}##
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2)
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; CHECK: r{{[0-9]+}}{{ *}}={{ *}}add(r{{[0-9]+}}{{ *}},{{ *}}r{{[0-9]+}})
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define i32 @test(i32 %y) nounwind {
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entry:
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switch i32 %y, label %sw.epilog [
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i32 1, label %sw.bb
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i32 2, label %sw.bb1
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i32 3, label %sw.bb2
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i32 4, label %sw.bb3
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i32 5, label %sw.bb4
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]
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sw.bb: ; preds = %entry
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tail call void bitcast (void (...)* @baz1 to void ()*)() nounwind
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br label %sw.epilog
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sw.bb1: ; preds = %entry
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tail call void @baz2(i32 2, i32 78) nounwind
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br label %sw.epilog
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sw.bb2: ; preds = %entry
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tail call void @baz3(i32 59) nounwind
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br label %sw.epilog
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sw.bb3: ; preds = %entry
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tail call void @baz4(i32 4, i32 14) nounwind
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br label %sw.epilog
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sw.bb4: ; preds = %entry
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br label %sw.epilog
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sw.epilog: ; preds = %sw.bb4, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb, %entry
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%y.addr.0 = phi i32 [ %y, %entry ], [ 14, %sw.bb4 ], [ 4, %sw.bb3 ], [ 3, %sw.bb2 ], [ 2, %sw.bb1 ], [ 1, %sw.bb ]
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ret i32 %y.addr.0
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}
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declare void @baz1(...)
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declare void @baz2(i32, i32)
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declare void @baz3(i32)
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declare void @baz4(i32, i32)
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