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llvm-mirror/test/CodeGen/SystemZ/fp-move-13.ll
Ulrich Weigand bc658bf60a [SystemZ] Add support for IBM z14 processor (3/3)
This adds support for the new 128-bit vector float instructions of z14.
Note that these instructions actually only operate on the f128 type,
since only each 128-bit vector register can hold only one 128-bit
float value.  However, this is still preferable to the legacy 128-bit
float instructions, since those operate on pairs of floating-point
registers (so we can hold at most 8 values in registers), while the
new instructions use single vector registers (so we hold up to 32
value in registers).

Adding support includes:
- Enabling the instructions for the assembler/disassembler.
- CodeGen for the instructions.  This includes allocating the f128
  type now to the VR128BitRegClass instead of FP128BitRegClass.
- Scheduler description support for the instructions.

Note that for a small number of operations, we have no new vector
instructions (like integer <-> 128-bit float conversions), and so
we use the legacy instruction and then reformat the operand
(i.e. copy between a pair of floating-point registers and a
vector register).

llvm-svn: 308196
2017-07-17 17:44:20 +00:00

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1.1 KiB
LLVM

; Test f128 moves on z14.
;
; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z14 | FileCheck %s
; VR-to-VR moves. Since f128s are passed by reference,
; we need to force a copy by other means.
define void @f1(fp128 *%x) {
; CHECK-LABEL: f1:
; CHECK: vlr
; CHECK: vleig
; CHECK: br %r14
%val = load volatile fp128 , fp128 *%x
%t1 = bitcast fp128 %val to <2 x i64>
%t2 = insertelement <2 x i64> %t1, i64 0, i32 0
%res = bitcast <2 x i64> %t2 to fp128
store volatile fp128 %res, fp128 *%x
store volatile fp128 %val, fp128 *%x
ret void
}
; Test 128-bit moves from GPRs to VRs. i128 isn't a legitimate type,
; so this goes through memory.
define void @f2(fp128 *%a, i128 *%b) {
; CHECK-LABEL: f2:
; CHECK: lg
; CHECK: lg
; CHECK: stg
; CHECK: stg
; CHECK: br %r14
%val = load i128 , i128 *%b
%res = bitcast i128 %val to fp128
store fp128 %res, fp128 *%a
ret void
}
; Test 128-bit moves from VRs to GPRs, with the same restriction as f2.
define void @f3(fp128 *%a, i128 *%b) {
; CHECK-LABEL: f3:
; CHECK: vl
; CHECK: vst
%val = load fp128 , fp128 *%a
%res = bitcast fp128 %val to i128
store i128 %res, i128 *%b
ret void
}