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b087bfb569
As discussed on D62910, we need to check whether particular types of memory access are allowed, not just their alignment/address-space. This NFC patch adds a MachineMemOperand::Flags argument to allowsMemoryAccess and allowsMisalignedMemoryAccesses, and wires up calls to pass the relevant flags to them. If people are happy with this approach I can then update X86TargetLowering::allowsMisalignedMemoryAccesses to handle misaligned NT load/stores. Differential Revision: https://reviews.llvm.org/D63075 llvm-svn: 363179
83 lines
3.3 KiB
C++
83 lines
3.3 KiB
C++
//===-- Mips16ISelLowering.h - Mips16 DAG Lowering Interface ----*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Subclass of MipsTargetLowering specialized for mips16.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_MIPS_MIPS16ISELLOWERING_H
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#define LLVM_LIB_TARGET_MIPS_MIPS16ISELLOWERING_H
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#include "MipsISelLowering.h"
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namespace llvm {
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class Mips16TargetLowering : public MipsTargetLowering {
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public:
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explicit Mips16TargetLowering(const MipsTargetMachine &TM,
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const MipsSubtarget &STI);
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bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AddrSpace,
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unsigned Align,
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MachineMemOperand::Flags Flags,
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bool *Fast) const override;
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MachineBasicBlock *
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EmitInstrWithCustomInserter(MachineInstr &MI,
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MachineBasicBlock *MBB) const override;
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private:
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bool isEligibleForTailCallOptimization(
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const CCState &CCInfo, unsigned NextStackOffset,
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const MipsFunctionInfo &FI) const override;
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void setMips16HardFloatLibCalls();
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unsigned int
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getMips16HelperFunctionStubNumber(ArgListTy &Args) const;
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const char *getMips16HelperFunction
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(Type* RetTy, ArgListTy &Args, bool &needHelper) const;
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void
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getOpndList(SmallVectorImpl<SDValue> &Ops,
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std::deque< std::pair<unsigned, SDValue> > &RegsToPass,
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bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage,
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bool IsCallReloc, CallLoweringInfo &CLI, SDValue Callee,
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SDValue Chain) const override;
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MachineBasicBlock *emitSel16(unsigned Opc, MachineInstr &MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitSeliT16(unsigned Opc1, unsigned Opc2,
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MachineInstr &MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitSelT16(unsigned Opc1, unsigned Opc2,
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MachineInstr &MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitFEXT_T8I816_ins(unsigned BtOpc, unsigned CmpOpc,
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MachineInstr &MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitFEXT_T8I8I16_ins(unsigned BtOpc, unsigned CmpiOpc,
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unsigned CmpiXOpc, bool ImmSigned,
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MachineInstr &MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitFEXT_CCRX16_ins(unsigned SltOpc, MachineInstr &MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *emitFEXT_CCRXI16_ins(unsigned SltiOpc, unsigned SltiXOpc,
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MachineInstr &MI,
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MachineBasicBlock *BB) const;
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};
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}
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#endif
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