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https://github.com/RPCS3/llvm-mirror.git
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e57810463a
We can end up with two loop exits whose exit counts are equivalent, but whose textual representation is different and non-obvious. For the sub-case where we have a series of exits which dominate one another (common), eliminate any exits which would iterate *after* a previous exit on the exiting iteration. As noted in the TODO being removed, I'd always thought this was a good idea, but I've now seen this in a real workload as well. Interestingly, in review, Nikita pointed out there's let another oppurtunity to leverage SCEV's reasoning. If we kept track of the min of dominanting exits so far, we could discharge exits with EC >= MDE. This is less powerful than the existing transform (since later exits aren't considered), but potentially more powerful for any case where SCEV can prove a >= b, but neither a == b or a > b. I don't have an example to illustrate that oppurtunity, but won't be suprised if we find one and return to handle that case as well. Differential Revision: https://reviews.llvm.org/D69009 llvm-svn: 375379
224 lines
7.3 KiB
LLVM
224 lines
7.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt -indvars -S < %s | FileCheck %s
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define void @ult(i64 %n, i64 %m) {
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; CHECK-LABEL: @ult(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP0:%.*]] = icmp ult i64 [[N:%.*]], [[M:%.*]]
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; CHECK-NEXT: br i1 [[CMP0]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
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; CHECK: loop.preheader:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[IV]], [[N]]
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; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: call void @side_effect()
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; CHECK-NEXT: br i1 true, label [[LOOP]], label [[EXIT_LOOPEXIT]]
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; CHECK: exit.loopexit:
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%cmp0 = icmp ult i64 %n, %m
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br i1 %cmp0, label %loop, label %exit
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ]
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%iv.next = add i64 %iv, 1
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%cmp1 = icmp ult i64 %iv, %n
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br i1 %cmp1, label %latch, label %exit
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latch:
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call void @side_effect()
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%cmp2 = icmp ult i64 %iv, %m
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br i1 %cmp2, label %loop, label %exit
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exit:
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ret void
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}
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define void @ugt(i64 %n, i64 %m) {
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; CHECK-LABEL: @ugt(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP0:%.*]] = icmp ugt i64 [[N:%.*]], [[M:%.*]]
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; CHECK-NEXT: br i1 [[CMP0]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
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; CHECK: loop.preheader:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: br i1 true, label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: call void @side_effect()
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[IV]], [[M]]
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; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[EXIT_LOOPEXIT]]
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; CHECK: exit.loopexit:
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%cmp0 = icmp ugt i64 %n, %m
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br i1 %cmp0, label %loop, label %exit
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ]
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%iv.next = add i64 %iv, 1
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%cmp1 = icmp ult i64 %iv, %n
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br i1 %cmp1, label %latch, label %exit
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latch:
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call void @side_effect()
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%cmp2 = icmp ult i64 %iv, %m
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br i1 %cmp2, label %loop, label %exit
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exit:
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ret void
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}
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define void @ule(i64 %n, i64 %m) {
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; CHECK-LABEL: @ule(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP0:%.*]] = icmp ule i64 [[N:%.*]], [[M:%.*]]
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; CHECK-NEXT: br i1 [[CMP0]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
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; CHECK: loop.preheader:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[IV]], [[N]]
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; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: call void @side_effect()
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[IV]], [[M]]
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; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[EXIT_LOOPEXIT]]
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; CHECK: exit.loopexit:
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%cmp0 = icmp ule i64 %n, %m
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br i1 %cmp0, label %loop, label %exit
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ]
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%iv.next = add i64 %iv, 1
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%cmp1 = icmp ult i64 %iv, %n
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br i1 %cmp1, label %latch, label %exit
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latch:
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call void @side_effect()
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%cmp2 = icmp ult i64 %iv, %m
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br i1 %cmp2, label %loop, label %exit
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exit:
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ret void
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}
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define void @uge(i64 %n, i64 %m) {
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; CHECK-LABEL: @uge(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP0:%.*]] = icmp uge i64 [[N:%.*]], [[M:%.*]]
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; CHECK-NEXT: br i1 [[CMP0]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
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; CHECK: loop.preheader:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[IV]], [[N]]
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; CHECK-NEXT: br i1 [[CMP1]], label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: call void @side_effect()
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[IV]], [[M]]
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; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[EXIT_LOOPEXIT]]
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; CHECK: exit.loopexit:
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%cmp0 = icmp uge i64 %n, %m
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br i1 %cmp0, label %loop, label %exit
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ]
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%iv.next = add i64 %iv, 1
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%cmp1 = icmp ult i64 %iv, %n
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br i1 %cmp1, label %latch, label %exit
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latch:
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call void @side_effect()
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%cmp2 = icmp ult i64 %iv, %m
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br i1 %cmp2, label %loop, label %exit
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exit:
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ret void
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}
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define void @ult_const_max(i64 %n) {
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; CHECK-LABEL: @ult_const_max(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[CMP0:%.*]] = icmp ult i64 [[N:%.*]], 20
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; CHECK-NEXT: br i1 [[CMP0]], label [[LOOP_PREHEADER:%.*]], label [[EXIT:%.*]]
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; CHECK: loop.preheader:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[IV_NEXT:%.*]], [[LATCH:%.*]] ], [ 0, [[LOOP_PREHEADER]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: br i1 true, label [[LATCH]], label [[EXIT_LOOPEXIT:%.*]]
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; CHECK: latch:
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; CHECK-NEXT: call void @side_effect()
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; CHECK-NEXT: [[CMP2:%.*]] = icmp ult i64 [[IV]], [[N]]
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; CHECK-NEXT: br i1 [[CMP2]], label [[LOOP]], label [[EXIT_LOOPEXIT]]
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; CHECK: exit.loopexit:
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; CHECK-NEXT: br label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%cmp0 = icmp ult i64 %n, 20
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br i1 %cmp0, label %loop, label %exit
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %latch ]
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%iv.next = add i64 %iv, 1
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%udiv = udiv i64 %iv, 10
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%cmp1 = icmp ult i64 %udiv, 2
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br i1 %cmp1, label %latch, label %exit
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latch:
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call void @side_effect()
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%cmp2 = icmp ult i64 %iv, %n
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br i1 %cmp2, label %loop, label %exit
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exit:
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ret void
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}
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define void @mixed_width(i32 %len) {
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; CHECK-LABEL: @mixed_width(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[LEN_ZEXT:%.*]] = zext i32 [[LEN:%.*]] to i64
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT:%.*]], [[BACKEDGE:%.*]] ]
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[CMP1:%.*]] = icmp ult i64 [[IV]], [[LEN_ZEXT]]
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; CHECK-NEXT: br i1 [[CMP1]], label [[BACKEDGE]], label [[EXIT:%.*]]
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; CHECK: backedge:
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; CHECK-NEXT: call void @side_effect()
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; CHECK-NEXT: br i1 true, label [[LOOP]], label [[EXIT]]
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; CHECK: exit:
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; CHECK-NEXT: ret void
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;
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entry:
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%len.zext = zext i32 %len to i64
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br label %loop
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loop:
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%iv = phi i64 [0, %entry], [%iv.next, %backedge]
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%iv2 = phi i32 [0, %entry], [%iv2.next, %backedge]
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%iv.next = add i64 %iv, 1
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%iv2.next = add i32 %iv2, 1
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%cmp1 = icmp ult i64 %iv, %len.zext
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br i1 %cmp1, label %backedge, label %exit
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backedge:
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call void @side_effect()
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%cmp2 = icmp ult i32 %iv2, %len
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br i1 %cmp2, label %loop, label %exit
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exit:
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ret void
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}
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declare void @side_effect()
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