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Summary: Calls sometimes need to be convergent. This is already handled at the LLVM IR level, but it also needs to be handled at the MI level. Ideally we'd propagate convergence from instructions, down through the selection DAG, and into MIs. But this is Hard, and would affect optimizations in the SDNs -- right now only SDNs with two operands have any flags at all. Instead, here's a much simpler hack: Add new opcodes for NVPTX for convergent calls, and generate these when lowering convergent LLVM calls. Reviewers: jholewinski Subscribers: jholewinski, chandlerc, joker.eph, jhen, tra, llvm-commits Differential Revision: http://reviews.llvm.org/D17423 llvm-svn: 262373
28 lines
620 B
LLVM
28 lines
620 B
LLVM
; RUN: llc -mtriple nvptx64-nvidia-cuda -stop-after machine-cp -o - < %s 2>&1 | FileCheck %s
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; Check that convergent calls are emitted using convergent MIR instructions,
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; while non-convergent calls are not.
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target triple = "nvptx64-nvidia-cuda"
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declare void @conv() convergent
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declare void @not_conv()
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define void @test(void ()* %f) {
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; CHECK: ConvergentCallUniPrintCall
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; CHECK-NEXT: @conv
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call void @conv()
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; CHECK: CallUniPrintCall
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; CHECK-NEXT: @not_conv
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call void @not_conv()
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; CHECK: ConvergentCallPrintCall
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call void %f() convergent
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; CHECK: CallPrintCall
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call void %f()
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ret void
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}
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