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https://github.com/RPCS3/llvm-mirror.git
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fc0fe5064b
vector type legalization strategies in a more fine grained manner, and change the legalization of several v1iN types and v1f32 to be widening rather than scalarization on AArch64. This fixes an assertion failure caused by scalarizing nodes like "v1i32 trunc v1i64". As v1i64 is legal it will fail to scalarize v1i32. This also provides a foundation for other targets to have more granular control over how vector types are legalized. Patch by Hao Liu, reviewed by Tim Northover. I'm committing it to allow some work to start taking place on top of this patch as it adds some really important hooks to the backend that I'd like to immediately start using. =] http://reviews.llvm.org/D4322 llvm-svn: 212242
207 lines
7.7 KiB
LLVM
207 lines
7.7 KiB
LLVM
; RUN: llc < %s -verify-machineinstrs -mtriple=arm64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s
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define <8x i8> @test_select_cc_v8i8_i8(i8 %a, i8 %b, <8x i8> %c, <8x i8> %d ) {
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; CHECK-LABEL: test_select_cc_v8i8_i8:
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; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
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; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
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; CHECK: cmeq [[MASK:v[0-9]+]].8b, v[[LHS]].8b, v[[RHS]].8b
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; CHECK: dup [[DUPMASK:v[0-9]+]].8b, [[MASK]].b[0]
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; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
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%cmp31 = icmp eq i8 %a, %b
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%e = select i1 %cmp31, <8x i8> %c, <8x i8> %d
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ret <8x i8> %e
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}
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define <8x i8> @test_select_cc_v8i8_f32(float %a, float %b, <8x i8> %c, <8x i8> %d ) {
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; CHECK-LABEL: test_select_cc_v8i8_f32:
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; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s
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; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0]
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; CHECK-NEXT: bsl [[DUPMASK]].8b, v2.8b, v3.8b
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%cmp31 = fcmp oeq float %a, %b
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%e = select i1 %cmp31, <8x i8> %c, <8x i8> %d
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ret <8x i8> %e
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}
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define <8x i8> @test_select_cc_v8i8_f64(double %a, double %b, <8x i8> %c, <8x i8> %d ) {
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; CHECK-LABEL: test_select_cc_v8i8_f64:
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; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1
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; CHECK-NEXT: bsl v[[MASK]].8b, v2.8b, v3.8b
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%cmp31 = fcmp oeq double %a, %b
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%e = select i1 %cmp31, <8x i8> %c, <8x i8> %d
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ret <8x i8> %e
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}
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define <16x i8> @test_select_cc_v16i8_i8(i8 %a, i8 %b, <16x i8> %c, <16x i8> %d ) {
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; CHECK-LABEL: test_select_cc_v16i8_i8:
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; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
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; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
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; CHECK: cmeq [[MASK:v[0-9]+]].16b, v[[LHS]].16b, v[[RHS]].16b
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; CHECK: dup [[DUPMASK:v[0-9]+]].16b, [[MASK]].b[0]
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; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
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%cmp31 = icmp eq i8 %a, %b
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%e = select i1 %cmp31, <16x i8> %c, <16x i8> %d
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ret <16x i8> %e
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}
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define <16x i8> @test_select_cc_v16i8_f32(float %a, float %b, <16x i8> %c, <16x i8> %d ) {
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; CHECK-LABEL: test_select_cc_v16i8_f32:
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; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s
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; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
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; CHECK-NEXT: bsl [[DUPMASK]].16b, v2.16b, v3.16b
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%cmp31 = fcmp oeq float %a, %b
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%e = select i1 %cmp31, <16x i8> %c, <16x i8> %d
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ret <16x i8> %e
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}
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define <16x i8> @test_select_cc_v16i8_f64(double %a, double %b, <16x i8> %c, <16x i8> %d ) {
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; CHECK-LABEL: test_select_cc_v16i8_f64:
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; CHECK: fcmeq [[MASK:v[0-9]+]].2d, v0.2d, v1.2d
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; CHECK-NEXT: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]
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; CHECK-NEXT: bsl [[DUPMASK]].16b, v2.16b, v3.16b
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%cmp31 = fcmp oeq double %a, %b
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%e = select i1 %cmp31, <16x i8> %c, <16x i8> %d
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ret <16x i8> %e
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}
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define <4x i16> @test_select_cc_v4i16(i16 %a, i16 %b, <4x i16> %c, <4x i16> %d ) {
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; CHECK-LABEL: test_select_cc_v4i16:
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; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
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; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
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; CHECK: cmeq [[MASK:v[0-9]+]].4h, v[[LHS]].4h, v[[RHS]].4h
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; CHECK: dup [[DUPMASK:v[0-9]+]].4h, [[MASK]].h[0]
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; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
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%cmp31 = icmp eq i16 %a, %b
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%e = select i1 %cmp31, <4x i16> %c, <4x i16> %d
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ret <4x i16> %e
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}
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define <8x i16> @test_select_cc_v8i16(i16 %a, i16 %b, <8x i16> %c, <8x i16> %d ) {
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; CHECK-LABEL: test_select_cc_v8i16:
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; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
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; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
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; CHECK: cmeq [[MASK:v[0-9]+]].8h, v[[LHS]].8h, v[[RHS]].8h
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; CHECK: dup [[DUPMASK:v[0-9]+]].8h, [[MASK]].h[0]
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; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
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%cmp31 = icmp eq i16 %a, %b
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%e = select i1 %cmp31, <8x i16> %c, <8x i16> %d
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ret <8x i16> %e
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}
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define <2x i32> @test_select_cc_v2i32(i32 %a, i32 %b, <2x i32> %c, <2x i32> %d ) {
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; CHECK-LABEL: test_select_cc_v2i32:
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; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
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; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
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; CHECK: cmeq [[MASK:v[0-9]+]].2s, v[[LHS]].2s, v[[RHS]].2s
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; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0]
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; CHECK: bsl [[DUPMASK]].8b, v0.8b, v1.8b
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%cmp31 = icmp eq i32 %a, %b
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%e = select i1 %cmp31, <2x i32> %c, <2x i32> %d
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ret <2x i32> %e
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}
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define <4x i32> @test_select_cc_v4i32(i32 %a, i32 %b, <4x i32> %c, <4x i32> %d ) {
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; CHECK-LABEL: test_select_cc_v4i32:
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; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
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; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
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; CHECK: cmeq [[MASK:v[0-9]+]].4s, v[[LHS]].4s, v[[RHS]].4s
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; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
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; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
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%cmp31 = icmp eq i32 %a, %b
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%e = select i1 %cmp31, <4x i32> %c, <4x i32> %d
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ret <4x i32> %e
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}
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define <1x i64> @test_select_cc_v1i64(i64 %a, i64 %b, <1x i64> %c, <1x i64> %d ) {
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; CHECK-LABEL: test_select_cc_v1i64:
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; CHECK-DAG: fmov d[[LHS:[0-9]+]], x0
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; CHECK-DAG: fmov d[[RHS:[0-9]+]], x1
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; CHECK: cmeq d[[MASK:[0-9]+]], d[[LHS]], d[[RHS]]
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; CHECK: bsl v[[MASK]].8b, v0.8b, v1.8b
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%cmp31 = icmp eq i64 %a, %b
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%e = select i1 %cmp31, <1x i64> %c, <1x i64> %d
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ret <1x i64> %e
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}
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define <2x i64> @test_select_cc_v2i64(i64 %a, i64 %b, <2x i64> %c, <2x i64> %d ) {
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; CHECK-LABEL: test_select_cc_v2i64:
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; CHECK-DAG: fmov d[[LHS:[0-9]+]], x0
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; CHECK-DAG: fmov d[[RHS:[0-9]+]], x1
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; CHECK: cmeq [[MASK:v[0-9]+]].2d, v[[LHS]].2d, v[[RHS]].2d
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; CHECK: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]
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; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
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%cmp31 = icmp eq i64 %a, %b
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%e = select i1 %cmp31, <2x i64> %c, <2x i64> %d
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ret <2x i64> %e
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}
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define <1 x float> @test_select_cc_v1f32(float %a, float %b, <1 x float> %c, <1 x float> %d ) {
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; CHECK-LABEL: test_select_cc_v1f32:
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; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s
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; CHECK-NEXT: bsl [[MASK]].8b, v2.8b, v3.8b
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%cmp31 = fcmp oeq float %a, %b
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%e = select i1 %cmp31, <1 x float> %c, <1 x float> %d
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ret <1 x float> %e
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}
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define <2 x float> @test_select_cc_v2f32(float %a, float %b, <2 x float> %c, <2 x float> %d ) {
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; CHECK-LABEL: test_select_cc_v2f32:
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; CHECK: fcmeq [[MASK:v[0-9]+]].2s, v0.2s, v1.2s
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; CHECK: dup [[DUPMASK:v[0-9]+]].2s, [[MASK]].s[0]
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; CHECK: bsl [[DUPMASK]].8b, v2.8b, v3.8b
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%cmp31 = fcmp oeq float %a, %b
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%e = select i1 %cmp31, <2 x float> %c, <2 x float> %d
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ret <2 x float> %e
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}
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define <4x float> @test_select_cc_v4f32(float %a, float %b, <4x float> %c, <4x float> %d ) {
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; CHECK-LABEL: test_select_cc_v4f32:
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; CHECK: fcmeq [[MASK:v[0-9]+]].4s, v0.4s, v1.4s
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; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
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; CHECK: bsl [[DUPMASK]].16b, v2.16b, v3.16b
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%cmp31 = fcmp oeq float %a, %b
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%e = select i1 %cmp31, <4x float> %c, <4x float> %d
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ret <4x float> %e
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}
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define <4x float> @test_select_cc_v4f32_icmp(i32 %a, i32 %b, <4x float> %c, <4x float> %d ) {
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; CHECK-LABEL: test_select_cc_v4f32_icmp:
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; CHECK-DAG: fmov s[[LHS:[0-9]+]], w0
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; CHECK-DAG: fmov s[[RHS:[0-9]+]], w1
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; CHECK: cmeq [[MASK:v[0-9]+]].4s, v[[LHS]].4s, v[[RHS]].4s
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; CHECK: dup [[DUPMASK:v[0-9]+]].4s, [[MASK]].s[0]
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; CHECK: bsl [[DUPMASK]].16b, v0.16b, v1.16b
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%cmp31 = icmp eq i32 %a, %b
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%e = select i1 %cmp31, <4x float> %c, <4x float> %d
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ret <4x float> %e
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}
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define <1 x double> @test_select_cc_v1f64(double %a, double %b, <1 x double> %c, <1 x double> %d ) {
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; CHECK-LABEL: test_select_cc_v1f64:
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; CHECK: fcmeq d[[MASK:[0-9]+]], d0, d1
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; CHECK: bsl v[[MASK]].8b, v2.8b, v3.8b
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%cmp31 = fcmp oeq double %a, %b
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%e = select i1 %cmp31, <1 x double> %c, <1 x double> %d
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ret <1 x double> %e
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}
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define <1 x double> @test_select_cc_v1f64_icmp(i64 %a, i64 %b, <1 x double> %c, <1 x double> %d ) {
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; CHECK-LABEL: test_select_cc_v1f64_icmp:
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; CHECK-DAG: fmov [[LHS:d[0-9]+]], x0
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; CHECK-DAG: fmov [[RHS:d[0-9]+]], x1
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; CHECK: cmeq d[[MASK:[0-9]+]], [[LHS]], [[RHS]]
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; CHECK: bsl v[[MASK]].8b, v0.8b, v1.8b
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%cmp31 = icmp eq i64 %a, %b
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%e = select i1 %cmp31, <1 x double> %c, <1 x double> %d
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ret <1 x double> %e
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}
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define <2 x double> @test_select_cc_v2f64(double %a, double %b, <2 x double> %c, <2 x double> %d ) {
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; CHECK-LABEL: test_select_cc_v2f64:
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; CHECK: fcmeq [[MASK:v[0-9]+]].2d, v0.2d, v1.2d
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; CHECK: dup [[DUPMASK:v[0-9]+]].2d, [[MASK]].d[0]
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; CHECK: bsl [[DUPMASK]].16b, v2.16b, v3.16b
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%cmp31 = fcmp oeq double %a, %b
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%e = select i1 %cmp31, <2 x double> %c, <2 x double> %d
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ret <2 x double> %e
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}
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