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llvm-mirror/test/MC/X86/mpx-encodings.s
Ahmed Bougacha 9d56162be1 [X86] Decode MPX BND registers.
We were able to assemble, but not disassemble.

Note that fixupRMValue was truncating EA_REG_BND0-3 because we hit
the uint8_t max.  The control registers were already squarely above
it, but I don't think they ever go in .r/m, only in .reg.

I also did notice an extra REX.W in our encoding, but I think that's
fine.

llvm-svn: 275427
2016-07-14 14:53:21 +00:00

42 lines
1.2 KiB
ArmAsm

// RUN: llvm-mc -triple x86_64-- -mattr=+mpx --show-encoding %s |\
// RUN: FileCheck %s --check-prefixes=CHECK,ENCODING
// RUN: llvm-mc -triple x86_64-- -mattr=+mpx -filetype=obj %s |\
// RUN: llvm-objdump -d - -mattr=+mpx | FileCheck %s
// CHECK: bndmk (%rax), %bnd0
// ENCODING: encoding: [0xf3,0x48,0x0f,0x1b,0x00]
bndmk (%rax), %bnd0
// CHECK: bndmk 1024(%rax), %bnd1
// ENCODING: encoding: [0xf3,0x48,0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
bndmk 1024(%rax), %bnd1
// CHECK: bndmov %bnd2, %bnd1
// ENCODING: encoding: [0x66,0x0f,0x1b,0xd1]
bndmov %bnd2, %bnd1
// CHECK: bndmov %bnd1, 1024(%r9)
// ENCODING: encoding: [0x66,0x49,0x0f,0x1b,0x89,0x00,0x04,0x00,0x00]
bndmov %bnd1, 1024(%r9)
// CHECK: bndstx %bnd1, 1024(%rax)
// ENCODING: encoding: [0x0f,0x1b,0x88,0x00,0x04,0x00,0x00]
bndstx %bnd1, 1024(%rax)
// CHECK: bndldx 1024(%r8), %bnd1
// ENCODING: encoding: [0x41,0x0f,0x1a,0x88,0x00,0x04,0x00,0x00]
bndldx 1024(%r8), %bnd1
// CHECK: bndcl 121(%r10), %bnd1
// ENCODING: encoding: [0xf3,0x49,0x0f,0x1a,0x4a,0x79]
bndcl 121(%r10), %bnd1
// CHECK: bndcn 121(%rcx), %bnd3
// ENCODING: encoding: [0xf2,0x48,0x0f,0x1b,0x59,0x79]
bndcn 121(%rcx), %bnd3
// CHECK: bndcu %rdx, %bnd3
// ENCODING: encoding: [0xf2,0x48,0x0f,0x1a,0xda]
bndcu %rdx, %bnd3