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99 lines
3.3 KiB
LLVM
99 lines
3.3 KiB
LLVM
; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
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; Test instrumentation of vector shift instructions.
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target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
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target triple = "x86_64-unknown-linux-gnu"
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declare x86_mmx @llvm.x86.mmx.psll.d(x86_mmx, x86_mmx)
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declare <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32>, <8 x i32>)
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declare <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32>, <4 x i32>)
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declare <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16>, <8 x i16>)
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declare <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16>, i32)
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define i64 @test_mmx(i64 %x.coerce, i64 %y.coerce) sanitize_memory {
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entry:
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%0 = bitcast i64 %x.coerce to <2 x i32>
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%1 = bitcast <2 x i32> %0 to x86_mmx
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%2 = bitcast i64 %y.coerce to x86_mmx
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%3 = tail call x86_mmx @llvm.x86.mmx.psll.d(x86_mmx %1, x86_mmx %2)
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%4 = bitcast x86_mmx %3 to <2 x i32>
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%5 = bitcast <2 x i32> %4 to <1 x i64>
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%6 = extractelement <1 x i64> %5, i32 0
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ret i64 %6
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}
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; CHECK-LABEL: @test_mmx
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; CHECK: = icmp ne i64 {{.*}}, 0
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; CHECK: [[C:%.*]] = sext i1 {{.*}} to i64
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; CHECK: [[A:%.*]] = call x86_mmx @llvm.x86.mmx.psll.d(
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; CHECK: [[B:%.*]] = bitcast x86_mmx {{.*}}[[A]] to i64
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; CHECK: = or i64 {{.*}}[[B]], {{.*}}[[C]]
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; CHECK: call x86_mmx @llvm.x86.mmx.psll.d(
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; CHECK: ret i64
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define <8 x i16> @test_sse2_scalar(<8 x i16> %x, i32 %y) sanitize_memory {
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entry:
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%0 = tail call <8 x i16> @llvm.x86.sse2.pslli.w(<8 x i16> %x, i32 %y)
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ret <8 x i16> %0
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}
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; CHECK-LABEL: @test_sse2_scalar
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; CHECK: = icmp ne i32 {{.*}}, 0
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; CHECK: = sext i1 {{.*}} to i128
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; CHECK: = bitcast i128 {{.*}} to <8 x i16>
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; CHECK: = call <8 x i16> @llvm.x86.sse2.pslli.w(
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; CHECK: = or <8 x i16>
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; CHECK: call <8 x i16> @llvm.x86.sse2.pslli.w(
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; CHECK: ret <8 x i16>
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define <8 x i16> @test_sse2(<8 x i16> %x, <8 x i16> %y) sanitize_memory {
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entry:
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%0 = tail call <8 x i16> @llvm.x86.sse2.psrl.w(<8 x i16> %x, <8 x i16> %y)
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ret <8 x i16> %0
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}
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; CHECK-LABEL: @test_sse2
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; CHECK: = bitcast <8 x i16> {{.*}} to i128
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; CHECK: = trunc i128 {{.*}} to i64
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; CHECK: = icmp ne i64 {{.*}}, 0
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; CHECK: = sext i1 {{.*}} to i128
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; CHECK: = bitcast i128 {{.*}} to <8 x i16>
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; CHECK: = call <8 x i16> @llvm.x86.sse2.psrl.w(
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; CHECK: = or <8 x i16>
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; CHECK: call <8 x i16> @llvm.x86.sse2.psrl.w(
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; CHECK: ret <8 x i16>
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; Test variable shift (i.e. vector by vector).
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define <4 x i32> @test_avx2(<4 x i32> %x, <4 x i32> %y) sanitize_memory {
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entry:
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%0 = tail call <4 x i32> @llvm.x86.avx2.psllv.d(<4 x i32> %x, <4 x i32> %y)
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ret <4 x i32> %0
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}
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; CHECK-LABEL: @test_avx2
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; CHECK: = icmp ne <4 x i32> {{.*}}, zeroinitializer
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; CHECK: = sext <4 x i1> {{.*}} to <4 x i32>
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; CHECK: = call <4 x i32> @llvm.x86.avx2.psllv.d(
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; CHECK: = or <4 x i32>
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; CHECK: = tail call <4 x i32> @llvm.x86.avx2.psllv.d(
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; CHECK: ret <4 x i32>
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define <8 x i32> @test_avx2_256(<8 x i32> %x, <8 x i32> %y) sanitize_memory {
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entry:
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%0 = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(<8 x i32> %x, <8 x i32> %y)
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ret <8 x i32> %0
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}
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; CHECK-LABEL: @test_avx2_256
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; CHECK: = icmp ne <8 x i32> {{.*}}, zeroinitializer
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; CHECK: = sext <8 x i1> {{.*}} to <8 x i32>
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; CHECK: = call <8 x i32> @llvm.x86.avx2.psllv.d.256(
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; CHECK: = or <8 x i32>
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; CHECK: = tail call <8 x i32> @llvm.x86.avx2.psllv.d.256(
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; CHECK: ret <8 x i32>
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