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be469fea7d
Summary:
Now that with D65143/D65144 we've produce `@llvm.umul.with.overflow`,
and with D65147 we've flattened the CFG, we now can see that
the guard may have been there to prevent division by zero is redundant.
We can simply drop it:
```
----------------------------------------
Name: no overflow or zero
%iszero = icmp eq i4 %y, 0
%umul = smul_overflow i4 %x, %y
%umul.ov = extractvalue {i4, i1} %umul, 1
%umul.ov.not = xor %umul.ov, -1
%retval.0 = or i1 %iszero, %umul.ov.not
ret i1 %retval.0
=>
%iszero = icmp eq i4 %y, 0
%umul = smul_overflow i4 %x, %y
%umul.ov = extractvalue {i4, i1} %umul, 1
%umul.ov.not = xor %umul.ov, -1
%retval.0 = or i1 %iszero, %umul.ov.not
ret i1 %umul.ov.not
Done: 1
Optimization is correct!
```
Note that this is inverted from what we have in a previous patch,
here we are looking for the inverted overflow bit.
And that inversion is kinda problematic - given this particular
pattern we neither hoist that `not` closer to `ret` (then the pattern
would have been identical to the one without inversion,
and would have been handled by the previous patch), neither
do the opposite transform. But regardless, we should handle this too.
I've filled [[ https://bugs.llvm.org/show_bug.cgi?id=42720 | PR42720 ]].
Reviewers: nikic, spatel, xbolva00, RKSimon
Reviewed By: spatel
Subscribers: hiraditya, llvm-commits
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D65151
llvm-svn: 370351
103 lines
4.1 KiB
LLVM
103 lines
4.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt %s -instsimplify -S | FileCheck %s
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declare { i4, i1 } @llvm.smul.with.overflow.i4(i4, i4) #1
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define i1 @t0_umul(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @t0_umul(
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: ret i1 [[PHITMP]]
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;
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%cmp = icmp eq i4 %size, 0
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}
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define i1 @t1_commutative(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @t1_commutative(
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE:%.*]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: ret i1 [[PHITMP]]
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;
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%cmp = icmp eq i4 %size, 0
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = or i1 %phitmp, %cmp ; swapped
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ret i1 %or
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}
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define i1 @n2_wrong_size(i4 %size0, i4 %size1, i4 %nmemb) {
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; CHECK-LABEL: @n2_wrong_size(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE1:%.*]], 0
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE0:%.*]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size1, 0 ; not %size0
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size0, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}
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define i1 @n3_wrong_pred(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @n3_wrong_pred(
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; CHECK-NEXT: [[CMP:%.*]] = icmp ne i4 [[SIZE:%.*]], 0
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp ne i4 %size, 0 ; not 'eq'
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}
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define i1 @n4_not_and(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @n4_not_and(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 0
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = and i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size, 0
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = and i1 %cmp, %phitmp ; not 'or'
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ret i1 %or
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}
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define i1 @n5_not_zero(i4 %size, i4 %nmemb) {
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; CHECK-LABEL: @n5_not_zero(
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i4 [[SIZE:%.*]], 1
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; CHECK-NEXT: [[SMUL:%.*]] = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 [[SIZE]], i4 [[NMEMB:%.*]])
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; CHECK-NEXT: [[SMUL_OV:%.*]] = extractvalue { i4, i1 } [[SMUL]], 1
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; CHECK-NEXT: [[PHITMP:%.*]] = xor i1 [[SMUL_OV]], true
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; CHECK-NEXT: [[OR:%.*]] = or i1 [[CMP]], [[PHITMP]]
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; CHECK-NEXT: ret i1 [[OR]]
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;
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%cmp = icmp eq i4 %size, 1 ; should be '0'
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%smul = tail call { i4, i1 } @llvm.smul.with.overflow.i4(i4 %size, i4 %nmemb)
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%smul.ov = extractvalue { i4, i1 } %smul, 1
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%phitmp = xor i1 %smul.ov, true
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%or = or i1 %cmp, %phitmp
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ret i1 %or
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}
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