Nirav Dave 0603cde0c8 [SDAG] Relax conditions under stores of loaded values can be merged ... Summary: Allow consecutive stores whose values come from consecutive loads to merged in the presense of other uses of the loads. Previously this was disallowed as in general the merged load cannot be shared with the other uses. Merging N stores into 1 may cause as many as N redundant loads. However in the context of caching this should have neglible affect on memory pressure and reduce instruction count making it almost always a win. Fixes PR32086. Reviewers: spatel, jyknight, andreadb, hfinkel, efriedma Reviewed By: efriedma Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D30471 llvm-svn: 302712		2017-05-10 19:53:41 +00:00
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AArch64	[AArch64][RegisterBankInfo] Change the default mapping of fp stores.	2017-05-10 15:19:41 +00:00
AMDGPU	[AMDGPU][MC] Corrected v_madak/madmk to avoid printing "_e32" in disassembler output	2017-05-10 13:00:28 +00:00
ARM	Add extra operand to CALLSEQ_START to keep frame part set up previously	2017-05-09 13:35:13 +00:00
AVR
BPF
Generic	Add a late IR expansion pass for the experimental reduction intrinsics.	2017-05-10 09:42:49 +00:00
Hexagon	Add extra operand to CALLSEQ_START to keep frame part set up previously	2017-05-09 13:35:13 +00:00
Inputs
Lanai	[lanai] Add computeKnownBitsForTargetNode for Lanai.	2017-05-09 18:35:26 +00:00
Mips	Revert "[MIPS] Add support to match more patterns for DINS instruction"	2017-05-09 13:18:48 +00:00
MIR	[IfConversion] Add missing check in IfConversion/canFallThroughTo	2017-05-10 13:06:13 +00:00
MSP430
NVPTX
PowerPC	Add extra operand to CALLSEQ_START to keep frame part set up previously	2017-05-09 13:35:13 +00:00
SPARC
SystemZ	[SystemZ] Implement getRepRegClassFor()	2017-05-10 13:03:25 +00:00
Thumb
Thumb2
WebAssembly
WinEH
X86	[SDAG] Relax conditions under stores of loaded values can be merged	2017-05-10 19:53:41 +00:00
XCore