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to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
49 lines
1.6 KiB
TableGen
49 lines
1.6 KiB
TableGen
//===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
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// slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS
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// slot has been removed.
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//
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//===----------------------------------------------------------------------===//
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def ALU_X : FuncUnit;
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def ALU_Y : FuncUnit;
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def ALU_Z : FuncUnit;
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def ALU_W : FuncUnit;
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def TRANS : FuncUnit;
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def AnyALU : InstrItinClass;
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def VecALU : InstrItinClass;
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def TransALU : InstrItinClass;
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def XALU : InstrItinClass;
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def R600_VLIW5_Itin : ProcessorItineraries <
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[ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS, ALU_NULL],
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[],
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[
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InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W, TRANS]>]>,
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InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
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InstrItinData<TransALU, [InstrStage<1, [TRANS]>]>,
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InstrItinData<XALU, [InstrStage<1, [ALU_X]>]>,
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InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
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]
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>;
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def R600_VLIW4_Itin : ProcessorItineraries <
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[ALU_X, ALU_Y, ALU_Z, ALU_W, ALU_NULL],
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[],
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[
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InstrItinData<AnyALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
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InstrItinData<VecALU, [InstrStage<1, [ALU_X, ALU_Y, ALU_Z, ALU_W]>]>,
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InstrItinData<TransALU, [InstrStage<1, [ALU_NULL]>]>,
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InstrItinData<NullALU, [InstrStage<1, [ALU_NULL]>]>
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]
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>;
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