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325 lines
10 KiB
C++
325 lines
10 KiB
C++
//===-- MipsISelDAGToDAG.cpp - A Dag to Dag Inst Selector for Mips --------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines an instruction selector for the MIPS target.
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//
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//===----------------------------------------------------------------------===//
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#include "MipsISelDAGToDAG.h"
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#include "MCTargetDesc/MipsBaseInfo.h"
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#include "Mips.h"
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#include "Mips16ISelDAGToDAG.h"
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#include "MipsMachineFunction.h"
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#include "MipsRegisterInfo.h"
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#include "MipsSEISelDAGToDAG.h"
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#include "llvm/CodeGen/MachineConstantPool.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/SelectionDAGNodes.h"
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#include "llvm/CodeGen/StackProtector.h"
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#include "llvm/IR/CFG.h"
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#include "llvm/IR/GlobalValue.h"
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#include "llvm/IR/Instructions.h"
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#include "llvm/IR/Intrinsics.h"
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#include "llvm/IR/Type.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/Target/TargetMachine.h"
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using namespace llvm;
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#define DEBUG_TYPE "mips-isel"
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//===----------------------------------------------------------------------===//
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// Instruction Selector Implementation
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// MipsDAGToDAGISel - MIPS specific code to select MIPS machine
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// instructions for SelectionDAG operations.
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//===----------------------------------------------------------------------===//
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void MipsDAGToDAGISel::getAnalysisUsage(AnalysisUsage &AU) const {
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// There are multiple MipsDAGToDAGISel instances added to the pass pipeline.
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// We need to preserve StackProtector for the next one.
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AU.addPreserved<StackProtector>();
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SelectionDAGISel::getAnalysisUsage(AU);
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}
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bool MipsDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
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Subtarget = &static_cast<const MipsSubtarget &>(MF.getSubtarget());
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bool Ret = SelectionDAGISel::runOnMachineFunction(MF);
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processFunctionAfterISel(MF);
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return Ret;
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}
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/// getGlobalBaseReg - Output the instructions required to put the
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/// GOT address into a register.
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SDNode *MipsDAGToDAGISel::getGlobalBaseReg() {
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Register GlobalBaseReg = MF->getInfo<MipsFunctionInfo>()->getGlobalBaseReg(*MF);
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return CurDAG->getRegister(GlobalBaseReg, getTargetLowering()->getPointerTy(
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CurDAG->getDataLayout()))
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.getNode();
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}
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/// ComplexPattern used on MipsInstrInfo
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/// Used on Mips Load/Store instructions
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bool MipsDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddr11MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddr12MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddr16MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrLSL2MM(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrSImm10(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl1(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl2(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectIntAddrSImm10Lsl3(SDValue Addr, SDValue &Base,
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SDValue &Offset) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectAddr16(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectAddr16SP(SDValue Addr, SDValue &Base,
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SDValue &Offset) {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm,
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unsigned MinSizeInBits) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatUimm1(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatUimm2(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatUimm3(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatUimm4(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatUimm5(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatUimm6(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatUimm8(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatSimm5(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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bool MipsDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
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llvm_unreachable("Unimplemented function.");
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return false;
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}
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/// Convert vector addition with vector subtraction if that allows to encode
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/// constant as an immediate and thus avoid extra 'ldi' instruction.
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/// add X, <-1, -1...> --> sub X, <1, 1...>
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bool MipsDAGToDAGISel::selectVecAddAsVecSubIfProfitable(SDNode *Node) {
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assert(Node->getOpcode() == ISD::ADD && "Should only get 'add' here.");
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EVT VT = Node->getValueType(0);
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assert(VT.isVector() && "Should only be called for vectors.");
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SDValue X = Node->getOperand(0);
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SDValue C = Node->getOperand(1);
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auto *BVN = dyn_cast<BuildVectorSDNode>(C);
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if (!BVN)
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return false;
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APInt SplatValue, SplatUndef;
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unsigned SplatBitSize;
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bool HasAnyUndefs;
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if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs,
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8, !Subtarget->isLittle()))
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return false;
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auto IsInlineConstant = [](const APInt &Imm) { return Imm.isIntN(5); };
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if (IsInlineConstant(SplatValue))
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return false; // Can already be encoded as an immediate.
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APInt NegSplatValue = 0 - SplatValue;
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if (!IsInlineConstant(NegSplatValue))
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return false; // Even if we negate it it won't help.
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SDLoc DL(Node);
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SDValue NegC = CurDAG->FoldConstantArithmetic(
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ISD::SUB, DL, VT, {CurDAG->getConstant(0, DL, VT), C});
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assert(NegC && "Constant-folding failed!");
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SDValue NewNode = CurDAG->getNode(ISD::SUB, DL, VT, X, NegC);
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ReplaceNode(Node, NewNode.getNode());
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SelectCode(NewNode.getNode());
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return true;
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}
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/// Select instructions not customized! Used for
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/// expanded, promoted and normal instructions
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void MipsDAGToDAGISel::Select(SDNode *Node) {
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unsigned Opcode = Node->getOpcode();
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// If we have a custom node, we already have selected!
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if (Node->isMachineOpcode()) {
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LLVM_DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
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Node->setNodeId(-1);
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return;
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}
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// See if subclasses can handle this node.
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if (trySelect(Node))
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return;
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switch(Opcode) {
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default: break;
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case ISD::ADD:
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if (Node->getSimpleValueType(0).isVector() &&
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selectVecAddAsVecSubIfProfitable(Node))
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return;
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break;
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// Get target GOT address.
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case ISD::GLOBAL_OFFSET_TABLE:
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ReplaceNode(Node, getGlobalBaseReg());
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return;
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#ifndef NDEBUG
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case ISD::LOAD:
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case ISD::STORE:
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assert((Subtarget->systemSupportsUnalignedAccess() ||
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cast<MemSDNode>(Node)->getMemoryVT().getSizeInBits() / 8 <=
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cast<MemSDNode>(Node)->getAlignment()) &&
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"Unexpected unaligned loads/stores.");
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break;
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#endif
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}
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// Select the default instruction
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SelectCode(Node);
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}
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bool MipsDAGToDAGISel::
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SelectInlineAsmMemoryOperand(const SDValue &Op, unsigned ConstraintID,
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std::vector<SDValue> &OutOps) {
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// All memory constraints can at least accept raw pointers.
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switch(ConstraintID) {
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default:
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llvm_unreachable("Unexpected asm memory constraint");
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case InlineAsm::Constraint_m:
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case InlineAsm::Constraint_R:
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case InlineAsm::Constraint_ZC:
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OutOps.push_back(Op);
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return false;
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}
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return true;
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}
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