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0e53532aeb
This patch teaches llvm-mca how to identify dependency breaking instructions on btver2. An example of dependency breaking instructions is the zero-idiom XOR (example: `XOR %eax, %eax`), which always generates zero regardless of the actual value of the input register operands. Dependency breaking instructions don't have to wait on their input register operands before executing. This is because the computation is not dependent on the inputs. Not all dependency breaking idioms are also zero-latency instructions. For example, `CMPEQ %xmm1, %xmm1` is independent on the value of XMM1, and it generates a vector of all-ones. That instruction is not eliminated at register renaming stage, and its opcode is issued to a pipeline for execution. So, the latency is not zero. This patch adds a new method named isDependencyBreaking() to the MCInstrAnalysis interface. That method takes as input an instruction (i.e. MCInst) and a MCSubtargetInfo. The default implementation of isDependencyBreaking() conservatively returns false for all instructions. Targets may override the default behavior for specific CPUs, and return a value which better matches the subtarget behavior. In future, we should teach to Tablegen how to automatically generate the body of isDependencyBreaking from scheduling predicate definitions. This would allow us to expose the knowledge about dependency breaking instructions to the machine schedulers (and, potentially, other codegen passes). Differential Revision: https://reviews.llvm.org/D49310 llvm-svn: 338372
42 lines
1.3 KiB
C++
42 lines
1.3 KiB
C++
//===- MCInstrAnalysis.cpp - InstrDesc target hooks -----------------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/MC/MCInstrAnalysis.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrDesc.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include <cstdint>
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using namespace llvm;
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bool MCInstrAnalysis::clearsSuperRegisters(const MCRegisterInfo &MRI,
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const MCInst &Inst,
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APInt &Writes) const {
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Writes.clearAllBits();
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return false;
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}
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bool MCInstrAnalysis::isDependencyBreaking(const MCSubtargetInfo &STI,
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const MCInst &Inst) const {
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return false;
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}
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bool MCInstrAnalysis::evaluateBranch(const MCInst &Inst, uint64_t Addr,
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uint64_t Size, uint64_t &Target) const {
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if (Inst.getNumOperands() == 0 ||
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Info->get(Inst.getOpcode()).OpInfo[0].OperandType != MCOI::OPERAND_PCREL)
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return false;
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int64_t Imm = Inst.getOperand(0).getImm();
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Target = Addr+Size+Imm;
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return true;
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}
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