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68c567a38a
The syntax for "cmpxchg" should now look something like: cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic where the second ordering argument gives the required semantics in the case that no exchange takes place. It should be no stronger than the first ordering constraint and cannot be either "release" or "acq_rel" (since no store will have taken place). rdar://problem/15996804 llvm-svn: 203559
209 lines
4.5 KiB
LLVM
209 lines
4.5 KiB
LLVM
; RUN: llc < %s -O0 -march=x86 -mcpu=corei7 -verify-machineinstrs | FileCheck %s --check-prefix X32
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@sc64 = external global i64
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define void @atomic_fetch_add64() nounwind {
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; X32: atomic_fetch_add64
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entry:
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%t1 = atomicrmw add i64* @sc64, i64 1 acquire
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; X32: addl
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; X32: adcl
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; X32: lock
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; X32: cmpxchg8b
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%t2 = atomicrmw add i64* @sc64, i64 3 acquire
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; X32: addl
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; X32: adcl
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; X32: lock
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; X32: cmpxchg8b
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%t3 = atomicrmw add i64* @sc64, i64 5 acquire
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; X32: addl
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; X32: adcl
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; X32: lock
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; X32: cmpxchg8b
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%t4 = atomicrmw add i64* @sc64, i64 %t3 acquire
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; X32: addl
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; X32: adcl
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_sub64() nounwind {
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; X32: atomic_fetch_sub64
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%t1 = atomicrmw sub i64* @sc64, i64 1 acquire
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; X32: subl
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; X32: sbbl
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; X32: lock
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; X32: cmpxchg8b
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%t2 = atomicrmw sub i64* @sc64, i64 3 acquire
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; X32: subl
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; X32: sbbl
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; X32: lock
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; X32: cmpxchg8b
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%t3 = atomicrmw sub i64* @sc64, i64 5 acquire
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; X32: subl
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; X32: sbbl
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; X32: lock
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; X32: cmpxchg8b
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%t4 = atomicrmw sub i64* @sc64, i64 %t3 acquire
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; X32: subl
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; X32: sbbl
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_and64() nounwind {
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; X32: atomic_fetch_and64
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%t1 = atomicrmw and i64* @sc64, i64 3 acquire
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; X32: andl
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; X32: andl
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; X32: lock
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; X32: cmpxchg8b
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%t2 = atomicrmw and i64* @sc64, i64 5 acquire
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; X32: andl
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; X32: andl
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; X32: lock
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; X32: cmpxchg8b
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%t3 = atomicrmw and i64* @sc64, i64 %t2 acquire
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; X32: andl
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; X32: andl
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_or64() nounwind {
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; X32: atomic_fetch_or64
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%t1 = atomicrmw or i64* @sc64, i64 3 acquire
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; X32: orl
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; X32: orl
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; X32: lock
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; X32: cmpxchg8b
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%t2 = atomicrmw or i64* @sc64, i64 5 acquire
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; X32: orl
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; X32: orl
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; X32: lock
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; X32: cmpxchg8b
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%t3 = atomicrmw or i64* @sc64, i64 %t2 acquire
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; X32: orl
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; X32: orl
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_xor64() nounwind {
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; X32: atomic_fetch_xor64
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%t1 = atomicrmw xor i64* @sc64, i64 3 acquire
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; X32: xorl
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; X32: xorl
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; X32: lock
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; X32: cmpxchg8b
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%t2 = atomicrmw xor i64* @sc64, i64 5 acquire
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; X32: xorl
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; X32: xorl
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; X32: lock
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; X32: cmpxchg8b
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%t3 = atomicrmw xor i64* @sc64, i64 %t2 acquire
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; X32: xorl
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; X32: xorl
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_nand64(i64 %x) nounwind {
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; X32: atomic_fetch_nand64
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%t1 = atomicrmw nand i64* @sc64, i64 %x acquire
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; X32: andl
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; X32: andl
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; X32: notl
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; X32: notl
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_max64(i64 %x) nounwind {
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%t1 = atomicrmw max i64* @sc64, i64 %x acquire
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; X32: cmpl
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; X32: cmpl
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; X32: cmov
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; X32: cmov
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; X32: cmov
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_min64(i64 %x) nounwind {
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%t1 = atomicrmw min i64* @sc64, i64 %x acquire
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; X32: cmpl
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; X32: cmpl
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; X32: cmov
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; X32: cmov
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; X32: cmov
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_umax64(i64 %x) nounwind {
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%t1 = atomicrmw umax i64* @sc64, i64 %x acquire
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; X32: cmpl
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; X32: cmpl
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; X32: cmov
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; X32: cmov
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; X32: cmov
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_umin64(i64 %x) nounwind {
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%t1 = atomicrmw umin i64* @sc64, i64 %x acquire
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; X32: cmpl
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; X32: cmpl
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; X32: cmov
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; X32: cmov
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; X32: cmov
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_cmpxchg64() nounwind {
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%t1 = cmpxchg i64* @sc64, i64 0, i64 1 acquire acquire
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_store64(i64 %x) nounwind {
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store atomic i64 %x, i64* @sc64 release, align 8
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; X32: lock
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; X32: cmpxchg8b
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ret void
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; X32: ret
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}
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define void @atomic_fetch_swap64(i64 %x) nounwind {
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%t1 = atomicrmw xchg i64* @sc64, i64 %x acquire
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; X32: lock
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; X32: xchg8b
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ret void
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; X32: ret
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}
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