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e3e67d4a0a
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
42 lines
995 B
LLVM
42 lines
995 B
LLVM
; RUN: llc < %s -mcpu=generic -march=x86 -enable-misched=false | FileCheck %s
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;; Simple case
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define i32 @test1(i8 %x) nounwind readnone {
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%A = and i8 %x, -32
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%B = zext i8 %A to i32
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ret i32 %B
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}
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; CHECK: test1
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; CHECK: movzbl
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; CHECK-NEXT: andl {{.*}}224
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;; Multiple uses of %x but easily extensible.
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define i32 @test2(i8 %x) nounwind readnone {
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%A = and i8 %x, -32
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%B = zext i8 %A to i32
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%C = or i8 %x, 63
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%D = zext i8 %C to i32
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%E = add i32 %B, %D
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ret i32 %E
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}
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; CHECK: test2
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; CHECK: movzbl
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; CHECK: andl $224
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; CHECK: orl $63
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declare void @use(i32, i8)
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;; Multiple uses of %x where we shouldn't extend the load.
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define void @test3(i8 %x) nounwind readnone {
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%A = and i8 %x, -32
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%B = zext i8 %A to i32
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call void @use(i32 %B, i8 %x)
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ret void
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}
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; CHECK: test3
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; CHECK: movzbl {{[0-9]+}}(%esp), [[REGISTER:%e[a-z]{2}]]
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; CHECK-NEXT: movl [[REGISTER]], 4(%esp)
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; CHECK-NEXT: andl $224, [[REGISTER]]
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; CHECK-NEXT: movl [[REGISTER]], (%esp)
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; CHECK-NEXT: call{{.*}}use
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