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4ef6d8fa15
cl = EXTRACT_SUBREG reg1024, 1, is overly conservative. It should check for overlaps of vr's live interval with the super registers of the physical register (ECX in this case) and let JoinIntervals() handle checking the coalescing feasibility against the physical register (cl in this case). llvm-svn: 98251
430 lines
18 KiB
C++
430 lines
18 KiB
C++
//===-- LiveIntervalAnalysis.h - Live Interval Analysis ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the LiveInterval analysis pass. Given some numbering of
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// each the machine instructions (in this implemention depth-first order) an
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// interval [i, j) is said to be a live interval for register v if there is no
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// instruction with number j' > j such that v is live at j' and there is no
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// instruction with number i' < i such that v is live at i'. In this
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// implementation intervals can have holes, i.e. an interval might look like
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// [1,20), [50,65), [1000,1001).
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#define LLVM_CODEGEN_LIVEINTERVAL_ANALYSIS_H
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#include "llvm/CodeGen/MachineBasicBlock.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/LiveInterval.h"
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#include "llvm/CodeGen/SlotIndexes.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/ADT/DenseMap.h"
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#include "llvm/ADT/SmallPtrSet.h"
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#include "llvm/ADT/SmallVector.h"
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#include "llvm/Support/Allocator.h"
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#include <cmath>
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#include <iterator>
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namespace llvm {
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class AliasAnalysis;
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class LiveVariables;
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class MachineLoopInfo;
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class TargetRegisterInfo;
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class MachineRegisterInfo;
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class TargetInstrInfo;
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class TargetRegisterClass;
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class VirtRegMap;
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class LiveIntervals : public MachineFunctionPass {
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MachineFunction* mf_;
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MachineRegisterInfo* mri_;
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const TargetMachine* tm_;
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const TargetRegisterInfo* tri_;
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const TargetInstrInfo* tii_;
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AliasAnalysis *aa_;
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LiveVariables* lv_;
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SlotIndexes* indexes_;
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/// Special pool allocator for VNInfo's (LiveInterval val#).
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///
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BumpPtrAllocator VNInfoAllocator;
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typedef DenseMap<unsigned, LiveInterval*> Reg2IntervalMap;
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Reg2IntervalMap r2iMap_;
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/// allocatableRegs_ - A bit vector of allocatable registers.
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BitVector allocatableRegs_;
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/// CloneMIs - A list of clones as result of re-materialization.
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std::vector<MachineInstr*> CloneMIs;
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public:
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static char ID; // Pass identification, replacement for typeid
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LiveIntervals() : MachineFunctionPass(&ID) {}
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// Calculate the spill weight to assign to a single instruction.
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static float getSpillWeight(bool isDef, bool isUse, unsigned loopDepth);
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// After summing the spill weights of all defs and uses, the final weight
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// should be normalized, dividing the weight of the interval by its size.
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// This encourages spilling of intervals that are large and have few uses,
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// and discourages spilling of small intervals with many uses.
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void normalizeSpillWeight(LiveInterval &li) {
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li.weight /= getApproximateInstructionCount(li) + 25;
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}
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typedef Reg2IntervalMap::iterator iterator;
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typedef Reg2IntervalMap::const_iterator const_iterator;
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const_iterator begin() const { return r2iMap_.begin(); }
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const_iterator end() const { return r2iMap_.end(); }
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iterator begin() { return r2iMap_.begin(); }
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iterator end() { return r2iMap_.end(); }
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unsigned getNumIntervals() const { return (unsigned)r2iMap_.size(); }
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LiveInterval &getInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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assert(I != r2iMap_.end() && "Interval does not exist for register");
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return *I->second;
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}
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const LiveInterval &getInterval(unsigned reg) const {
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Reg2IntervalMap::const_iterator I = r2iMap_.find(reg);
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assert(I != r2iMap_.end() && "Interval does not exist for register");
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return *I->second;
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}
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bool hasInterval(unsigned reg) const {
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return r2iMap_.count(reg);
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}
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/// getScaledIntervalSize - get the size of an interval in "units,"
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/// where every function is composed of one thousand units. This
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/// measure scales properly with empty index slots in the function.
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double getScaledIntervalSize(LiveInterval& I) {
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return (1000.0 * I.getSize()) / indexes_->getIndexesLength();
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}
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/// getApproximateInstructionCount - computes an estimate of the number
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/// of instructions in a given LiveInterval.
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unsigned getApproximateInstructionCount(LiveInterval& I) {
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double IntervalPercentage = getScaledIntervalSize(I) / 1000.0;
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return (unsigned)(IntervalPercentage * indexes_->getFunctionSize());
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}
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/// conflictsWithPhysReg - Returns true if the specified register is used or
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/// defined during the duration of the specified interval. Copies to and
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/// from li.reg are allowed. This method is only able to analyze simple
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/// ranges that stay within a single basic block. Anything else is
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/// considered a conflict.
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bool conflictsWithPhysReg(const LiveInterval &li, VirtRegMap &vrm,
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unsigned reg);
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/// conflictsWithSubPhysRegRef - Similar to conflictsWithPhysRegRef except
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/// it checks for sub-register reference and it can check use as well.
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bool conflictsWithSubPhysRegRef(LiveInterval &li, unsigned Reg,
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bool CheckUse,
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SmallPtrSet<MachineInstr*,32> &JoinedCopies);
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// Interval creation
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LiveInterval &getOrCreateInterval(unsigned reg) {
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Reg2IntervalMap::iterator I = r2iMap_.find(reg);
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if (I == r2iMap_.end())
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I = r2iMap_.insert(std::make_pair(reg, createInterval(reg))).first;
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return *I->second;
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}
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/// dupInterval - Duplicate a live interval. The caller is responsible for
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/// managing the allocated memory.
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LiveInterval *dupInterval(LiveInterval *li);
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/// addLiveRangeToEndOfBlock - Given a register and an instruction,
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/// adds a live range from that instruction to the end of its MBB.
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LiveRange addLiveRangeToEndOfBlock(unsigned reg,
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MachineInstr* startInst);
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// Interval removal
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void removeInterval(unsigned Reg) {
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DenseMap<unsigned, LiveInterval*>::iterator I = r2iMap_.find(Reg);
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delete I->second;
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r2iMap_.erase(I);
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}
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SlotIndex getZeroIndex() const {
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return indexes_->getZeroIndex();
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}
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SlotIndex getInvalidIndex() const {
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return indexes_->getInvalidIndex();
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}
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/// isNotInMIMap - returns true if the specified machine instr has been
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/// removed or was never entered in the map.
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bool isNotInMIMap(const MachineInstr* Instr) const {
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return !indexes_->hasIndex(Instr);
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}
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/// Returns the base index of the given instruction.
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SlotIndex getInstructionIndex(const MachineInstr *instr) const {
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return indexes_->getInstructionIndex(instr);
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}
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/// Returns the instruction associated with the given index.
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MachineInstr* getInstructionFromIndex(SlotIndex index) const {
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return indexes_->getInstructionFromIndex(index);
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}
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/// Return the first index in the given basic block.
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SlotIndex getMBBStartIdx(const MachineBasicBlock *mbb) const {
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return indexes_->getMBBStartIdx(mbb);
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}
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/// Return the last index in the given basic block.
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SlotIndex getMBBEndIdx(const MachineBasicBlock *mbb) const {
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return indexes_->getMBBEndIdx(mbb);
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}
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MachineBasicBlock* getMBBFromIndex(SlotIndex index) const {
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return indexes_->getMBBFromIndex(index);
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}
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SlotIndex getMBBTerminatorGap(const MachineBasicBlock *mbb) {
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return indexes_->getTerminatorGap(mbb);
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}
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SlotIndex InsertMachineInstrInMaps(MachineInstr *MI) {
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return indexes_->insertMachineInstrInMaps(MI);
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}
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void RemoveMachineInstrFromMaps(MachineInstr *MI) {
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indexes_->removeMachineInstrFromMaps(MI);
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}
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void ReplaceMachineInstrInMaps(MachineInstr *MI, MachineInstr *NewMI) {
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indexes_->replaceMachineInstrInMaps(MI, NewMI);
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}
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bool findLiveInMBBs(SlotIndex Start, SlotIndex End,
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SmallVectorImpl<MachineBasicBlock*> &MBBs) const {
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return indexes_->findLiveInMBBs(Start, End, MBBs);
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}
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void renumber() {
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indexes_->renumberIndexes();
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}
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BumpPtrAllocator& getVNInfoAllocator() { return VNInfoAllocator; }
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/// getVNInfoSourceReg - Helper function that parses the specified VNInfo
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/// copy field and returns the source register that defines it.
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unsigned getVNInfoSourceReg(const VNInfo *VNI) const;
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virtual void getAnalysisUsage(AnalysisUsage &AU) const;
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virtual void releaseMemory();
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/// runOnMachineFunction - pass entry point
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virtual bool runOnMachineFunction(MachineFunction&);
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/// print - Implement the dump method.
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virtual void print(raw_ostream &O, const Module* = 0) const;
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/// addIntervalsForSpills - Create new intervals for spilled defs / uses of
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/// the given interval. FIXME: It also returns the weight of the spill slot
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/// (if any is created) by reference. This is temporary.
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std::vector<LiveInterval*>
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addIntervalsForSpills(const LiveInterval& i,
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SmallVectorImpl<LiveInterval*> &SpillIs,
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const MachineLoopInfo *loopInfo, VirtRegMap& vrm);
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/// addIntervalsForSpillsFast - Quickly create new intervals for spilled
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/// defs / uses without remat or splitting.
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std::vector<LiveInterval*>
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addIntervalsForSpillsFast(const LiveInterval &li,
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const MachineLoopInfo *loopInfo, VirtRegMap &vrm);
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/// spillPhysRegAroundRegDefsUses - Spill the specified physical register
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/// around all defs and uses of the specified interval. Return true if it
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/// was able to cut its interval.
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bool spillPhysRegAroundRegDefsUses(const LiveInterval &li,
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unsigned PhysReg, VirtRegMap &vrm);
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/// isReMaterializable - Returns true if every definition of MI of every
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/// val# of the specified interval is re-materializable. Also returns true
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/// by reference if all of the defs are load instructions.
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bool isReMaterializable(const LiveInterval &li,
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SmallVectorImpl<LiveInterval*> &SpillIs,
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bool &isLoad);
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/// isReMaterializable - Returns true if the definition MI of the specified
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/// val# of the specified interval is re-materializable.
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bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
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MachineInstr *MI);
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/// getRepresentativeReg - Find the largest super register of the specified
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/// physical register.
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unsigned getRepresentativeReg(unsigned Reg) const;
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/// getNumConflictsWithPhysReg - Return the number of uses and defs of the
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/// specified interval that conflicts with the specified physical register.
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unsigned getNumConflictsWithPhysReg(const LiveInterval &li,
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unsigned PhysReg) const;
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/// processImplicitDefs - Process IMPLICIT_DEF instructions. Add isUndef
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/// marker to implicit_def defs and their uses.
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void processImplicitDefs();
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/// intervalIsInOneMBB - Returns true if the specified interval is entirely
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/// within a single basic block.
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bool intervalIsInOneMBB(const LiveInterval &li) const;
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private:
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/// computeIntervals - Compute live intervals.
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void computeIntervals();
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/// handleRegisterDef - update intervals for a register def
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/// (calls handlePhysicalRegisterDef and
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/// handleVirtualRegisterDef)
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void handleRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI,
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SlotIndex MIIdx,
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MachineOperand& MO, unsigned MOIdx);
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/// handleVirtualRegisterDef - update intervals for a virtual
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/// register def
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void handleVirtualRegisterDef(MachineBasicBlock *MBB,
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MachineBasicBlock::iterator MI,
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SlotIndex MIIdx, MachineOperand& MO,
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unsigned MOIdx,
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LiveInterval& interval);
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/// handlePhysicalRegisterDef - update intervals for a physical register
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/// def.
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void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
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MachineBasicBlock::iterator mi,
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SlotIndex MIIdx, MachineOperand& MO,
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LiveInterval &interval,
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MachineInstr *CopyMI);
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/// handleLiveInRegister - Create interval for a livein register.
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void handleLiveInRegister(MachineBasicBlock* mbb,
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SlotIndex MIIdx,
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LiveInterval &interval, bool isAlias = false);
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/// getReMatImplicitUse - If the remat definition MI has one (for now, we
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/// only allow one) virtual register operand, then its uses are implicitly
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/// using the register. Returns the virtual register.
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unsigned getReMatImplicitUse(const LiveInterval &li,
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MachineInstr *MI) const;
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/// isValNoAvailableAt - Return true if the val# of the specified interval
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/// which reaches the given instruction also reaches the specified use
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/// index.
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bool isValNoAvailableAt(const LiveInterval &li, MachineInstr *MI,
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SlotIndex UseIdx) const;
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/// isReMaterializable - Returns true if the definition MI of the specified
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/// val# of the specified interval is re-materializable. Also returns true
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/// by reference if the def is a load.
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bool isReMaterializable(const LiveInterval &li, const VNInfo *ValNo,
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MachineInstr *MI,
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SmallVectorImpl<LiveInterval*> &SpillIs,
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bool &isLoad);
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/// tryFoldMemoryOperand - Attempts to fold either a spill / restore from
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/// slot / to reg or any rematerialized load into ith operand of specified
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/// MI. If it is successul, MI is updated with the newly created MI and
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/// returns true.
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bool tryFoldMemoryOperand(MachineInstr* &MI, VirtRegMap &vrm,
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MachineInstr *DefMI, SlotIndex InstrIdx,
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SmallVector<unsigned, 2> &Ops,
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bool isSS, int FrameIndex, unsigned Reg);
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/// canFoldMemoryOperand - Return true if the specified load / store
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/// folding is possible.
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bool canFoldMemoryOperand(MachineInstr *MI,
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SmallVector<unsigned, 2> &Ops,
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bool ReMatLoadSS) const;
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/// anyKillInMBBAfterIdx - Returns true if there is a kill of the specified
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/// VNInfo that's after the specified index but is within the basic block.
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bool anyKillInMBBAfterIdx(const LiveInterval &li, const VNInfo *VNI,
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MachineBasicBlock *MBB,
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SlotIndex Idx) const;
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/// hasAllocatableSuperReg - Return true if the specified physical register
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/// has any super register that's allocatable.
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bool hasAllocatableSuperReg(unsigned Reg) const;
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/// SRInfo - Spill / restore info.
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struct SRInfo {
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SlotIndex index;
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unsigned vreg;
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bool canFold;
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SRInfo(SlotIndex i, unsigned vr, bool f)
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: index(i), vreg(vr), canFold(f) {}
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};
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bool alsoFoldARestore(int Id, SlotIndex index, unsigned vr,
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BitVector &RestoreMBBs,
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DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
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void eraseRestoreInfo(int Id, SlotIndex index, unsigned vr,
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BitVector &RestoreMBBs,
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DenseMap<unsigned,std::vector<SRInfo> >&RestoreIdxes);
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/// handleSpilledImpDefs - Remove IMPLICIT_DEF instructions which are being
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/// spilled and create empty intervals for their uses.
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void handleSpilledImpDefs(const LiveInterval &li, VirtRegMap &vrm,
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const TargetRegisterClass* rc,
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std::vector<LiveInterval*> &NewLIs);
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/// rewriteImplicitOps - Rewrite implicit use operands of MI (i.e. uses of
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/// interval on to-be re-materialized operands of MI) with new register.
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void rewriteImplicitOps(const LiveInterval &li,
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MachineInstr *MI, unsigned NewVReg, VirtRegMap &vrm);
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/// rewriteInstructionForSpills, rewriteInstructionsForSpills - Helper
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/// functions for addIntervalsForSpills to rewrite uses / defs for the given
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/// live range.
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bool rewriteInstructionForSpills(const LiveInterval &li, const VNInfo *VNI,
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bool TrySplit, SlotIndex index, SlotIndex end,
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MachineInstr *MI, MachineInstr *OrigDefMI, MachineInstr *DefMI,
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unsigned Slot, int LdSlot,
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bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
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VirtRegMap &vrm, const TargetRegisterClass* rc,
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SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
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unsigned &NewVReg, unsigned ImpUse, bool &HasDef, bool &HasUse,
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DenseMap<unsigned,unsigned> &MBBVRegsMap,
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std::vector<LiveInterval*> &NewLIs);
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void rewriteInstructionsForSpills(const LiveInterval &li, bool TrySplit,
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LiveInterval::Ranges::const_iterator &I,
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MachineInstr *OrigDefMI, MachineInstr *DefMI, unsigned Slot, int LdSlot,
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bool isLoad, bool isLoadSS, bool DefIsReMat, bool CanDelete,
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VirtRegMap &vrm, const TargetRegisterClass* rc,
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SmallVector<int, 4> &ReMatIds, const MachineLoopInfo *loopInfo,
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BitVector &SpillMBBs,
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DenseMap<unsigned,std::vector<SRInfo> > &SpillIdxes,
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BitVector &RestoreMBBs,
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DenseMap<unsigned,std::vector<SRInfo> > &RestoreIdxes,
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DenseMap<unsigned,unsigned> &MBBVRegsMap,
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std::vector<LiveInterval*> &NewLIs);
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// Normalize the spill weight of all the intervals in NewLIs.
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void normalizeSpillWeights(std::vector<LiveInterval*> &NewLIs);
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static LiveInterval* createInterval(unsigned Reg);
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void printInstrs(raw_ostream &O) const;
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void dumpInstrs() const;
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};
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} // End llvm namespace
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#endif
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