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1660c0bc25
The DAGCombiner folds the zext into complex load instructions. This patch prevents this optimization on vectors since none of the supported targets knows how to perform load+vector_zext in one instruction. llvm-svn: 126080
70 lines
1.6 KiB
LLVM
70 lines
1.6 KiB
LLVM
; RUN: llc < %s -march=x86-64
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; PR 9267
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define<4 x i32> @func_16_32() {
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%F = load <4 x i16>* undef
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%G = zext <4 x i16> %F to <4 x i32>
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%H = load <4 x i16>* undef
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%Y = zext <4 x i16> %H to <4 x i32>
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%T = add <4 x i32> %Y, %G
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store <4 x i32>%T , <4 x i32>* undef
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ret <4 x i32> %T
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}
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define<4 x i64> @func_16_64() {
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%F = load <4 x i16>* undef
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%G = zext <4 x i16> %F to <4 x i64>
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%H = load <4 x i16>* undef
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%Y = zext <4 x i16> %H to <4 x i64>
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%T = xor <4 x i64> %Y, %G
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store <4 x i64>%T , <4 x i64>* undef
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ret <4 x i64> %T
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}
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define<4 x i64> @func_32_64() {
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%F = load <4 x i32>* undef
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%G = zext <4 x i32> %F to <4 x i64>
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%H = load <4 x i32>* undef
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%Y = zext <4 x i32> %H to <4 x i64>
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%T = or <4 x i64> %Y, %G
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ret <4 x i64> %T
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}
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define<4 x i16> @func_8_16() {
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%F = load <4 x i8>* undef
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%G = zext <4 x i8> %F to <4 x i16>
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%H = load <4 x i8>* undef
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%Y = zext <4 x i8> %H to <4 x i16>
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%T = add <4 x i16> %Y, %G
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ret <4 x i16> %T
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}
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define<4 x i32> @func_8_32() {
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%F = load <4 x i8>* undef
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%G = zext <4 x i8> %F to <4 x i32>
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%H = load <4 x i8>* undef
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%Y = zext <4 x i8> %H to <4 x i32>
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%T = sub <4 x i32> %Y, %G
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ret <4 x i32> %T
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}
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define<4 x i64> @func_8_64() {
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%F = load <4 x i8>* undef
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%G = zext <4 x i8> %F to <4 x i64>
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%H = load <4 x i8>* undef
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%Y = zext <4 x i8> %H to <4 x i64>
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%T = add <4 x i64> %Y, %G
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ret <4 x i64> %T
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}
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define<4 x i32> @const_16_32() {
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%G = zext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i32>
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ret <4 x i32> %G
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}
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define<4 x i64> @const_16_64() {
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%G = zext <4 x i16> <i16 0, i16 3, i16 8, i16 7> to <4 x i64>
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ret <4 x i64> %G
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}
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