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mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-23 21:13:02 +02:00
llvm-mirror/test/CodeGen
Ron Lieberman 4789174868 Fix unsupported relocation type R_HEX_6_X' for symbol .rodata
LowerTargetConstantPool is not properly setting the TargetFlag to indicate
desired relocation. Coding error, the offset parameter was omitted, so the
TargetFlag was used as the offset, and the TargetFlag defaulted to zero.

This only affects -fpic compilation, and only those items created in a
Constant Pool, for example a vector of constants. Halide ran into this issue.

llvm-svn: 278614
2016-08-13 23:41:11 +00:00
..
AArch64 [AArch64LoadStoreOptimizer] Check aliasing correctly when creating paired loads/stores. 2016-08-12 20:39:51 +00:00
AMDGPU Revert "Revert "Invariant start/end intrinsics overloaded for address space"" 2016-08-13 23:31:24 +00:00
ARM Reapply [BranchFolding] Restrict tail merging loop blocks after MBP 2016-08-12 23:13:38 +00:00
BPF
Generic
Hexagon Fix unsupported relocation type R_HEX_6_X' for symbol .rodata 2016-08-13 23:41:11 +00:00
Inputs
Lanai
Mips
MIR
MSP430
NVPTX [NVPTX] Use untyped (.b) integer registers in PTX. 2016-08-12 22:02:19 +00:00
PowerPC Codegen: Don't tail-duplicate blocks with un-analyzable fallthrough. 2016-08-10 21:03:27 +00:00
SPARC Revert "[Sparc] Leon errata fix passes." 2016-08-12 14:48:09 +00:00
SystemZ
Thumb
Thumb2 CodeGen: If Convert blocks that would form a diamond when tail-merged. 2016-08-10 20:45:56 +00:00
WebAssembly [WebAssembly] Re-enable disabled debug value test 2016-08-12 23:14:18 +00:00
WinEH
X86 [x86] add tests to show missed 64-bit immediate merging 2016-08-13 18:42:14 +00:00
XCore