..
Analysis
[CostModel][AArch64] Improve cost model for vector reduction intrinsics
2021-06-24 12:02:58 +01:00
Assembler
IR: Fix use-list-order round-tripping for call and invoke
2021-06-23 12:04:19 -07:00
Bindings
Bitcode
[BitcodeReader] Validate Strtab before accessing.
2021-06-22 14:52:16 +01:00
BugPoint
CodeGen
[PowerPC] Combine 64-bit bswap(load) without LDBRX
2021-06-24 15:11:47 -05:00
DebugInfo
[DebugInfo] Enable variadic debug value salvaging
2021-06-24 13:16:29 +01:00
Demangle
[Demangle][Rust] Parse dot suffix
2021-06-18 09:29:45 +02:00
Examples
ExecutionEngine
[JITLink][MachO] Add missing testcase.
2021-06-13 20:43:49 +10:00
Feature
FileCheck
Instrumentation
[hwasan] Respect llvm.asan.globals.
2021-06-23 18:37:00 -07:00
Integer
JitListener
Linker
[IR] convert warn-stack-size from module flag to fn attr
2021-06-21 15:09:25 -07:00
LTO
MachineVerifier
MC
[AMDGPU] Add gfx1035 target
2021-06-24 14:32:41 -04:00
Object
[AMDGPU] Add gfx1035 target
2021-06-24 14:32:41 -04:00
ObjectYAML
[WebAssembly] Rename event to tag
2021-06-17 20:34:19 -07:00
Other
[OpaquePtr] Introduce option to force all pointers to be opaque pointers
2021-06-24 13:32:31 -07:00
SafepointIRVerifier
Support
SymbolRewriter
TableGen
[TableGen] Fix printing second PC-relative operand
2021-06-23 13:27:37 +07:00
ThinLTO /X86
tools
[AMDGPU] Add gfx1035 target
2021-06-24 14:32:41 -04:00
Transforms
[InstCombine] Make indexed compare fold opaque ptr compatible
2021-06-24 22:33:01 +02:00
Unit
Verifier
[OpaquePtr] Mangle intrinsics with opaque pointers arguments
2021-06-23 10:52:13 -07:00
YAMLParser
.clang-format
CMakeLists.txt
[IRSim] Adding basic implementation of llvm-sim.
2021-06-23 14:38:58 -05:00
lit.cfg.py
[IRSim] Adding basic implementation of llvm-sim.
2021-06-23 14:38:58 -05:00
lit.site.cfg.py.in
Make lit configs relocatable again after c747b7d1d9a
2021-06-22 15:27:32 -04:00
TestRunner.sh