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c7495a0fca
Add a mapping from register-based <INSN>R instructions to the corresponding memory-based <INSN>. Use it to cut down on the number of spill loads. Some instructions extend their operands from smaller fields, so this required a new TSFlags field to say how big the unextended operand is. This optimisation doesn't trigger for C(G)R and CL(G)R because in practice we always combine those instructions with a branch. Adding a test for every other case probably seems excessive, but it did catch a missed optimisation for DSGF (fixed in r185435). llvm-svn: 185529
191 lines
5.0 KiB
LLVM
191 lines
5.0 KiB
LLVM
; Test zero extensions from an i32 to an i64.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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; Test register extension, starting with an i32.
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define i64 @f1(i32 %a) {
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; CHECK: f1:
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; CHECK: llgfr %r2, %r2
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; CHECK: br %r14
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%ext = zext i32 %a to i64
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ret i64 %ext
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}
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; ...and again with an i64.
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define i64 @f2(i64 %a) {
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; CHECK: f2:
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; CHECK: llgfr %r2, %r2
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; CHECK: br %r14
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%word = trunc i64 %a to i32
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check ANDs that are equivalent to zero extension.
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define i64 @f3(i64 %a) {
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; CHECK: f3:
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; CHECK: llgfr %r2, %r2
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; CHECK: br %r14
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%ext = and i64 %a, 4294967295
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ret i64 %ext
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}
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; Check LLGF with no displacement.
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define i64 @f4(i32 *%src) {
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; CHECK: f4:
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; CHECK: llgf %r2, 0(%r2)
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; CHECK: br %r14
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%word = load i32 *%src
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check the high end of the LLGF range.
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define i64 @f5(i32 *%src) {
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; CHECK: f5:
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; CHECK: llgf %r2, 524284(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131071
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%word = load i32 *%ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f6(i32 *%src) {
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; CHECK: f6:
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; CHECK: agfi %r2, 524288
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; CHECK: llgf %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 131072
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%word = load i32 *%ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check the high end of the negative LLGF range.
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define i64 @f7(i32 *%src) {
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; CHECK: f7:
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; CHECK: llgf %r2, -4(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -1
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%word = load i32 *%ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check the low end of the LLGF range.
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define i64 @f8(i32 *%src) {
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; CHECK: f8:
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; CHECK: llgf %r2, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131072
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%word = load i32 *%ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define i64 @f9(i32 *%src) {
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; CHECK: f9:
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; CHECK: agfi %r2, -524292
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; CHECK: llgf %r2, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i32 *%src, i64 -131073
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%word = load i32 *%ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Check that LLGF allows an index.
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define i64 @f10(i64 %src, i64 %index) {
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; CHECK: f10:
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; CHECK: llgf %r2, 524287(%r3,%r2)
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i32 *
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%word = load i32 *%ptr
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%ext = zext i32 %word to i64
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ret i64 %ext
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}
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; Test a case where we spill the source of at least one LLGFR. We want
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; to use LLGF if possible.
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define void @f11(i64 *%ptr1, i32 *%ptr2) {
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; CHECK: f11:
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; CHECK: llgf {{%r[0-9]+}}, 16{{[04]}}(%r15)
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; CHECK: br %r14
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%val0 = load volatile i32 *%ptr2
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%val1 = load volatile i32 *%ptr2
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%val2 = load volatile i32 *%ptr2
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%val3 = load volatile i32 *%ptr2
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%val4 = load volatile i32 *%ptr2
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%val5 = load volatile i32 *%ptr2
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%val6 = load volatile i32 *%ptr2
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%val7 = load volatile i32 *%ptr2
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%val8 = load volatile i32 *%ptr2
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%val9 = load volatile i32 *%ptr2
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%val10 = load volatile i32 *%ptr2
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%val11 = load volatile i32 *%ptr2
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%val12 = load volatile i32 *%ptr2
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%val13 = load volatile i32 *%ptr2
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%val14 = load volatile i32 *%ptr2
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%val15 = load volatile i32 *%ptr2
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%ext0 = zext i32 %val0 to i64
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%ext1 = zext i32 %val1 to i64
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%ext2 = zext i32 %val2 to i64
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%ext3 = zext i32 %val3 to i64
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%ext4 = zext i32 %val4 to i64
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%ext5 = zext i32 %val5 to i64
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%ext6 = zext i32 %val6 to i64
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%ext7 = zext i32 %val7 to i64
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%ext8 = zext i32 %val8 to i64
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%ext9 = zext i32 %val9 to i64
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%ext10 = zext i32 %val10 to i64
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%ext11 = zext i32 %val11 to i64
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%ext12 = zext i32 %val12 to i64
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%ext13 = zext i32 %val13 to i64
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%ext14 = zext i32 %val14 to i64
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%ext15 = zext i32 %val15 to i64
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store volatile i32 %val0, i32 *%ptr2
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store volatile i32 %val1, i32 *%ptr2
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store volatile i32 %val2, i32 *%ptr2
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store volatile i32 %val3, i32 *%ptr2
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store volatile i32 %val4, i32 *%ptr2
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store volatile i32 %val5, i32 *%ptr2
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store volatile i32 %val6, i32 *%ptr2
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store volatile i32 %val7, i32 *%ptr2
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store volatile i32 %val8, i32 *%ptr2
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store volatile i32 %val9, i32 *%ptr2
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store volatile i32 %val10, i32 *%ptr2
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store volatile i32 %val11, i32 *%ptr2
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store volatile i32 %val12, i32 *%ptr2
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store volatile i32 %val13, i32 *%ptr2
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store volatile i32 %val14, i32 *%ptr2
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store volatile i32 %val15, i32 *%ptr2
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store volatile i64 %ext0, i64 *%ptr1
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store volatile i64 %ext1, i64 *%ptr1
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store volatile i64 %ext2, i64 *%ptr1
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store volatile i64 %ext3, i64 *%ptr1
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store volatile i64 %ext4, i64 *%ptr1
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store volatile i64 %ext5, i64 *%ptr1
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store volatile i64 %ext6, i64 *%ptr1
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store volatile i64 %ext7, i64 *%ptr1
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store volatile i64 %ext8, i64 *%ptr1
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store volatile i64 %ext9, i64 *%ptr1
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store volatile i64 %ext10, i64 *%ptr1
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store volatile i64 %ext11, i64 *%ptr1
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store volatile i64 %ext12, i64 *%ptr1
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store volatile i64 %ext13, i64 *%ptr1
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store volatile i64 %ext14, i64 *%ptr1
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store volatile i64 %ext15, i64 *%ptr1
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ret void
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}
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