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231 lines
7.8 KiB
TableGen
231 lines
7.8 KiB
TableGen
//===-- AVRRegisterInfo.td - AVR Register defs -------------*- tablegen -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the AVR register file
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//===----------------------------------------------------------------------===//
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// 8-bit General purpose register definition.
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class AVRReg<bits<16> num,
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string name,
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list<Register> subregs = [],
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list<string> altNames = []>
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: RegisterWithSubRegs<name, subregs>
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{
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field bits<16> Num = num;
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let HWEncoding = num;
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let Namespace = "AVR";
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let SubRegs = subregs;
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let AltNames = altNames;
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}
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// Subregister indices.
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let Namespace = "AVR" in
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{
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def sub_lo : SubRegIndex<8>;
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def sub_hi : SubRegIndex<8, 8>;
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}
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let Namespace = "AVR" in {
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def ptr : RegAltNameIndex;
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}
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//===----------------------------------------------------------------------===//
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// 8-bit general purpose registers
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//===----------------------------------------------------------------------===//
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def R0 : AVRReg<0, "r0">, DwarfRegNum<[0]>;
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def R1 : AVRReg<1, "r1">, DwarfRegNum<[1]>;
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def R2 : AVRReg<2, "r2">, DwarfRegNum<[2]>;
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def R3 : AVRReg<3, "r3">, DwarfRegNum<[3]>;
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def R4 : AVRReg<4, "r4">, DwarfRegNum<[4]>;
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def R5 : AVRReg<5, "r5">, DwarfRegNum<[5]>;
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def R6 : AVRReg<6, "r6">, DwarfRegNum<[6]>;
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def R7 : AVRReg<7, "r7">, DwarfRegNum<[7]>;
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def R8 : AVRReg<8, "r8">, DwarfRegNum<[8]>;
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def R9 : AVRReg<9, "r9">, DwarfRegNum<[9]>;
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def R10 : AVRReg<10, "r10">, DwarfRegNum<[10]>;
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def R11 : AVRReg<11, "r11">, DwarfRegNum<[11]>;
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def R12 : AVRReg<12, "r12">, DwarfRegNum<[12]>;
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def R13 : AVRReg<13, "r13">, DwarfRegNum<[13]>;
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def R14 : AVRReg<14, "r14">, DwarfRegNum<[14]>;
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def R15 : AVRReg<15, "r15">, DwarfRegNum<[15]>;
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def R16 : AVRReg<16, "r16">, DwarfRegNum<[16]>;
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def R17 : AVRReg<17, "r17">, DwarfRegNum<[17]>;
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def R18 : AVRReg<18, "r18">, DwarfRegNum<[18]>;
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def R19 : AVRReg<19, "r19">, DwarfRegNum<[19]>;
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def R20 : AVRReg<20, "r20">, DwarfRegNum<[20]>;
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def R21 : AVRReg<21, "r21">, DwarfRegNum<[21]>;
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def R22 : AVRReg<22, "r22">, DwarfRegNum<[22]>;
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def R23 : AVRReg<23, "r23">, DwarfRegNum<[23]>;
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def R24 : AVRReg<24, "r24">, DwarfRegNum<[24]>;
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def R25 : AVRReg<25, "r25">, DwarfRegNum<[25]>;
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def R26 : AVRReg<26, "r26">, DwarfRegNum<[26]>;
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def R27 : AVRReg<27, "r27">, DwarfRegNum<[27]>;
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def R28 : AVRReg<28, "r28">, DwarfRegNum<[28]>;
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def R29 : AVRReg<29, "r29">, DwarfRegNum<[29]>;
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def R30 : AVRReg<30, "r30">, DwarfRegNum<[30]>;
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def R31 : AVRReg<31, "r31">, DwarfRegNum<[31]>;
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def SPL : AVRReg<32, "SPL">, DwarfRegNum<[32]>;
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def SPH : AVRReg<33, "SPH">, DwarfRegNum<[33]>;
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let SubRegIndices = [sub_lo, sub_hi],
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CoveredBySubRegs = 1 in
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{
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// 16 bit GPR pairs.
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def SP : AVRReg<32, "SP", [SPL, SPH]>, DwarfRegNum<[32]>;
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// The pointer registers (X,Y,Z) are a special case because they
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// are printed as a `high:low` pair when a DREG is expected,
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// but printed using `X`, `Y`, `Z` when a pointer register is expected.
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let RegAltNameIndices = [ptr] in {
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def R31R30 : AVRReg<30, "r31:r30", [R30, R31], ["Z"]>, DwarfRegNum<[30]>;
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def R29R28 : AVRReg<28, "r29:r28", [R28, R29], ["Y"]>, DwarfRegNum<[28]>;
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def R27R26 : AVRReg<26, "r27:r26", [R26, R27], ["X"]>, DwarfRegNum<[26]>;
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}
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def R25R24 : AVRReg<24, "r25:r24", [R24, R25]>, DwarfRegNum<[24]>;
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def R23R22 : AVRReg<22, "r23:r22", [R22, R23]>, DwarfRegNum<[22]>;
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def R21R20 : AVRReg<20, "r21:r20", [R20, R21]>, DwarfRegNum<[20]>;
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def R19R18 : AVRReg<18, "r19:r18", [R18, R19]>, DwarfRegNum<[18]>;
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def R17R16 : AVRReg<16, "r17:r16", [R16, R17]>, DwarfRegNum<[16]>;
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def R15R14 : AVRReg<14, "r15:r14", [R14, R15]>, DwarfRegNum<[14]>;
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def R13R12 : AVRReg<12, "r13:r12", [R12, R13]>, DwarfRegNum<[12]>;
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def R11R10 : AVRReg<10, "r11:r10", [R10, R11]>, DwarfRegNum<[10]>;
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def R9R8 : AVRReg<8, "r9:r8", [R8, R9]>, DwarfRegNum<[8]>;
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def R7R6 : AVRReg<6, "r7:r6", [R6, R7]>, DwarfRegNum<[6]>;
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def R5R4 : AVRReg<4, "r5:r4", [R4, R5]>, DwarfRegNum<[4]>;
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def R3R2 : AVRReg<2, "r3:r2", [R2, R3]>, DwarfRegNum<[2]>;
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def R1R0 : AVRReg<0, "r1:r0", [R0, R1]>, DwarfRegNum<[0]>;
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}
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//===----------------------------------------------------------------------===//
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// Register Classes
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//===----------------------------------------------------------------------===//
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// Main 8-bit register class.
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def GPR8 : RegisterClass<"AVR", [i8], 8,
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(
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// Return value and argument registers.
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add R24, R25, R18, R19, R20, R21, R22, R23,
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// Scratch registers.
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R30, R31, R26, R27,
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// Callee saved registers.
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R28, R29, R17, R16, R15, R14, R13, R12, R11, R10,
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R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
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)>;
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// Simple lower registers r0..r15
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def GPR8lo : RegisterClass<"AVR", [i8], 8,
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(
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add R15, R14, R13, R12, R11, R10, R9, R8, R7, R6, R5, R4, R3, R2, R0, R1
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)>;
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// 8-bit register class for instructions which take immediates.
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def LD8 : RegisterClass<"AVR", [i8], 8,
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(
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// Return value and arguments.
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add R24, R25, R18, R19, R20, R21, R22, R23,
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// Scratch registers.
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R30, R31, R26, R27,
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// Callee saved registers.
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R28, R29, R17, R16
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)>;
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// Simple lower registers r16..r23
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def LD8lo : RegisterClass<"AVR", [i8], 8,
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(
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add R23, R22, R21, R20, R19, R18, R17, R16
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)>;
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// Main 16-bit pair register class.
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def DREGS : RegisterClass<"AVR", [i16], 8,
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(
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// Return value and arguments.
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add R25R24, R19R18, R21R20, R23R22,
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// Scratch registers.
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R31R30, R27R26,
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// Callee saved registers.
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R29R28, R17R16, R15R14, R13R12, R11R10,
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R9R8, R7R6, R5R4, R3R2, R1R0
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)>;
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// The 16-bit DREGS register class, excluding the Z pointer register.
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//
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// This is used by instructions which cause high pointer register
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// contention which leads to an assertion in the register allocator.
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//
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// There is no technical reason why instructions that use this class
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// cannot use Z; it's simply a workaround a regalloc bug.
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//
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// More information can be found in PR39553.
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def DREGS_WITHOUT_Z_WORKAROUND : RegisterClass<"AVR", [i16], 8,
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(
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// Return value and arguments.
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add R25R24, R19R18, R21R20, R23R22,
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// Scratch registers.
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R27R26,
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// Callee saved registers.
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R29R28, R17R16, R15R14, R13R12, R11R10,
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R9R8, R7R6, R5R4, R3R2, R1R0
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)>;
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// 16-bit register class for immediate instructions.
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def DLDREGS : RegisterClass<"AVR", [i16], 8,
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(
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// Return value and arguments.
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add R25R24, R19R18, R21R20, R23R22,
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// Scratch registers.
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R31R30, R27R26,
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// Callee saved registers.
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R29R28, R17R16
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)>;
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// 16-bit register class for the adiw/sbiw instructions.
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def IWREGS : RegisterClass<"AVR", [i16], 8,
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(
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// Return value and arguments.
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add R25R24,
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// Scratch registers.
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R31R30, R27R26,
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// Callee saved registers.
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R29R28
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)>;
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// 16-bit register class for the ld and st instructions.
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// AKA X,Y, and Z
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def PTRREGS : RegisterClass<"AVR", [i16], 8,
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(
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add R27R26, // X
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R29R28, // Y
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R31R30 // Z
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), ptr>;
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// 16-bit register class for the ldd and std instructions.
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// AKA Y and Z.
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def PTRDISPREGS : RegisterClass<"AVR", [i16], 8,
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(
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add R31R30, R29R28
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), ptr>;
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// We have a bunch of instructions with an explicit Z register argument. We
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// model this using a register class containing only the Z register.
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def ZREG : RegisterClass<"AVR", [i16], 8, (add R31R30)>;
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// Register class used for the stack read pseudo instruction.
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def GPRSP: RegisterClass<"AVR", [i16], 8, (add SP)>;
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// Status register.
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def SREG : AVRReg<14, "FLAGS">, DwarfRegNum<[88]>;
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def CCR : RegisterClass<"AVR", [i8], 8, (add SREG)>
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{
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let CopyCost = -1; // Don't allow copying of status registers
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}
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