Simon Pilgrim 47d7a9344e [X86] Remove shift/rotate by CL memory (RMW) overrides ... The uops are slightly different to the register variant, so requires a +1uop tweak llvm-svn: 342916		2018-09-24 20:11:50 +00:00
..
Analysis
Assembler	[test] Fix Assembler/debug-info.ll	2018-09-21 12:28:44 +00:00
Bindings
Bitcode	Fix some missing opcodes in bcanalyzer	2018-09-24 12:47:17 +00:00
BugPoint
CodeGen	[X86] Remove shift/rotate by CL memory (RMW) overrides	2018-09-24 20:11:50 +00:00
DebugInfo	[NativePDB] Add support for reading function signatures.	2018-09-21 22:36:28 +00:00
Demangle
Examples
ExecutionEngine
Feature
FileCheck
Instrumentation
Integer
JitListener
Linker	Fix asserts when linking wrong address space declarations	2018-09-24 04:42:14 +00:00
LTO	Pass code-model through Module IR to LTO which will use it.	2018-09-21 18:41:31 +00:00
MC	[Arm][AsmParser] Restrict register list size for VSTM/VLDM	2018-09-24 15:13:48 +00:00
Object
ObjectYAML
Other	[New PM][PassInstrumentation] IR printing support for New Pass Manager	2018-09-24 16:08:15 +00:00
SafepointIRVerifier
SymbolRewriter
TableGen
ThinLTO/X86	[ThinLTO] Write TYPE_IDs for types used in functions imported by aliases	2018-09-19 18:51:42 +00:00
tools	[X86] Remove shift/rotate by CL memory (RMW) overrides	2018-09-24 20:11:50 +00:00
Transforms	Reland r342494 after fixing LIT checks.	2018-09-24 17:26:30 +00:00
Unit
Verifier
YAMLParser
.clang-format
CMakeLists.txt
lit.cfg.py
lit.site.cfg.py.in
TestRunner.sh