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c2d91820e1
Add the prefixed instructions pld and pstd to future CPU. These are load and store instructions that require new operand types that are 34 bits. This patch adds the two instructions as well as the operand types required. Note that this patch also makes a minor change to tablegen to account for the fact that some instructions are going to require shifts greater than 31 bits for the new 34 bit instructions. Differential Revision: https://reviews.llvm.org/D72574
20 lines
639 B
LLVM
20 lines
639 B
LLVM
; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
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; RUN: -mtriple=powerpc64le-unknown-unknown -ppc-asm-full-reg-names \
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; RUN: %s -o - 2>&1 | FileCheck %s
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; RUN: llc -mattr=pcrelative-memops,prefix-instrs -verify-machineinstrs \
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; RUN: -mtriple=powerpc64-unknown-unknown -ppc-asm-full-reg-names \
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; RUN: %s -o - 2>&1 | FileCheck %s
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define dso_local signext i32 @f() {
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entry:
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ret i32 0
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}
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; Make sure that all of the features listed are recognized.
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; CHECK-NOT: is not a recognized feature for this target
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; Make sure that the test was actually compiled.
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; CHECK: li r3, 0
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; CHECK-NEXT: blr
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